View STV2050A_801835.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STV2050A
AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR
s
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Multiscan 1H, 2H, HDTV and SVGA applications 6 Convergence channels 14-bit embedded DACs 1 Focus channel Second order interpolation in vertical direction Digital filtering in horizontal direction On-chip PLL On-chip video pattern generator Automatic compensation of temperature drift and aging of external components Pattern and synchronisation signals for optional optical sensor support Adjustable horizontal and vertical size Up to 7 different data sets Self-controlled power-on sequence
Package: PQFP80 Power Supply: 3.3 V Tape and Reel: STV2050ATR
Figure 1. Functional Block Diagram
RAM H/V Sync Frame and Line Timebase Security Control
Horizontal and Vertical Defection Corrections
HR HG HB
VR VG VB Focus R G B
Focus
IC Control
EEPROM Interface
Pattern Generator
September 2003
1/83
Table of Contents
1 GENERAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 SYSTEM BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 DEVICE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 APPLICATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 PIN DESCRIPTION AND PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 STRUCTURE OF THE PROGRAMMING SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 DATA STORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 OVERVIEW OF EMBEDDED RAM ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 ADJUSTMENT DATA SETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 SLAVE IC BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 ADS0: IC Address and PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 SCLS Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 SDAI Bus Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 SDAO Bus Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 COLOR BANK SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 15
3.3 WRITE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 READ COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 IC I/O LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 RAM ALLOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 CONVERGENCE CORRECTION VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 Dynamic Correction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 Common Correction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 IC REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 Registers Storable in the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Registers Not Storable in the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TIMEBASES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 LINE LOCKED PLL AND SYSTEM CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 21 21
5.2 SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 HORIZONTAL TIMEBASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.1 Horizontal DAC Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Horizontal Width Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Auto-Calibration of DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 VERTICAL TIME BASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Vertical Synchronization Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Field Parity Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Field Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Convergence Correction Frame Retrace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MASTER IC BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 READ OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 24 24 25 25 25 27 28
6.2 WRITE OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 POWER-ON SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 83 6.4 SECURITY FEATURE DURING DATA TRANFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 STATUS INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Table of Contents
6.6 DATA TRANSFER BETWEEN RAM AND EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 MASTER CLOCK FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 VIDEO PATTERN GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 GENERAL FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.1 Pattern Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.2 Pattern Visibility Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 CROSS-HATCH GRID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.1 Horizontal Grid Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.2 Vertical Grid Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 CURSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.1 Cursor Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.2 Cursor Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 BORDER LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.1 Border Lines: Left / Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.2 Border Lines: Bottom / Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 GAIN ADJUSTMENT LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5.1 Video Pattern for Horizontal Gain Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5.2 Video Pattern for Vertical Gain Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.6 AUTO-ALIGNMENT PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 BLANKING OF VIDEO SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 HORIZONTAL BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 VERTICAL BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 BLANKING FOR AUTO-ALIGNMENT PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4 FAST BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 CONVERGENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 GLOBAL ADJUSTMENTS - COMMON PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.1 Position Offset (also called "static") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Field Offset Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 DYNAMIC VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 46 46
9.3 INTERLACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4 CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5 INTERPOLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5.1 Vertical Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5.2 Horizontal Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.6 NORMAL TV OPERATION MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.7 MANUFACTURING, AFTER-SALES SERVICE, LAB TRIAL MODES . . . . . . . . . . . . . . . 48 9.7.1 Output of Field Offset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.2 Gain and Offset Measuring Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.3 Gain Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.4 Field Offset Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 CONVERGENCE OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 49 49 50
10 DYNAMIC FOCUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 PARABOLA CURVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STV2050A 10.2 FOCUS OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 ELECTRICAL LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 PRINCIPLE OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 LOOP PARAMETER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 LOOP STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 OPERATION OF THE ELECTRICAL LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5 OUTPUT/INPUT PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5.1PORA, PORB and PORC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2OGAH and OGAV Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 OPTICAL LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 PRINCIPAL OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 57 58 58
12.2 OPTT SENSOR PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2.1OPTT Pin used as an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.2OPTT Pin used as an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3 OPTI SENSOR STATUS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13 CURRENT REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14 SECURITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.2 HAMMING ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.3 SECURITY OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 15 BOOT SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IC STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 BUS EXPANDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RECOMMANDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 63 64 64 64 64 64
20.2 CURRENT REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.3 VIDEO PATTERN OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.3.1DACs for RGB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.3.2FBLK Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.4 FOCUS DACS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.4.1Focus Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.4.2Focus Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.5 CONVERGENCE DACS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.6 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.7 MASTER IC TIME BASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.8 HORIZONTAL AND VERTICAL SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . 67 20.9 TBU OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 20.10ELECTRICAL LOOP PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 22 ELECTRICAL PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23 IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION . . . . . . . . . . . . . 72
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STV2050A 24 INDEX OF IC BUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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2
STV2050A - GENERAL OVERVIEW
1 GENERAL OVERVIEW
1.1 SYSTEM BLOCK DIAGRAM Figure 2. TV Set Convergence System Diagram
Tuner
Convergence Application Circuit
h v
IF Video
Sound
EEPROM(s)
H/V Deflection
bl R G B
Power Stage
6x h v
To/From Microprocessor
IC Bus
R G B GND R G B GND R G B GND R G B GND Focus
R G
h v
Focus Amplifier
1x
B
h v
6/83
STV2050A - GENERAL OVERVIEW
GNDG
GNDB
VCCB
VCCP
VCCM GNDM
GNDQ
GNDH
VCCA
GNDC
GNDD
GNDN
VCCH
VCCC
VCCG
GNDP
GNDA
GNDF
VCCQ
GNDK
VCCD
VCCN
VCCF
VCCK
GNDL
GNDJ
VCCL
VCCJ
Analog Power Supplies
SDAO SDAI SCLS ADS0 SDAM SCLM OSCL GRES IC Oscillator
400 khz Blue Memory Green Memory
Digital Power Supplies
DAC Calibration Logic
IC Slave
Memory Control
Red Memory
14
D
DARV
A
Interpolation
Gain/Offset
DNRV
14
D
DAGV
A
DNGV
IC Master
Vertical Filters
14
D
A
DABV DNBV
14
D
DARH
A
Start Logic
14 DAC Enable
D
DNRH DAGH
A
DNGH
FLT2 FILT
PLL
PLL Logic
Focus Processor
Focus
Loop
Horizontal Filters
14
D
DABH
A
DNBH
6 System Clock System Reset Parallel IC Bus Memory Register Bus
Figure 3. STV2050A Block Diagram
SYNH ECLK SYNV REST Vertical Filter
D
A
FOCS
Timebase
DAC Timing Vsync Grid Timing
1.2 DEVICE BLOCK DIAGRAM
Video Pattern Generator
011111h
6
D
A
FOCR
IREF
REFC
BUS Expander Port Interface
4
4
4
OGAV D A A D A D
OGAH
Bandgap
OPTT PORC
REFN
PORB
PORA
VIDB
POUT
VIDG
VBLK
TBU7
TBU6
TBU5
TBU4
TBU3
TBU2
TBU1
TBU0
OPTI
TEST
MLIN
VIDR
7/83
STV2050A - GENERAL OVERVIEW 1.3 APPLICATION CIRCUIT An application circuit with 2nd EEPROM, Electrical Offset and Gain Adjustment Loop and Optical Sensors is shown in the following figure. Figure 4. Application Circuit
3.3 V Analog 3.3 V Digital 19 VCCD 44 VCCG 42 VCCH 31 VCCJ 6 VCCK 32 VCCL 73 VCCM 12 VCCN 5 VCCQ 43 GNDG 41 GNDH 29 GNDJ 4 GNDK 30 GNDL 76 GNDM 15 GNDN 3 GNDQ 71 ADS0 8 SDAI 7 SDAO CLK 3.3 V M24164 3.3 V 1 2 3 8 7 6 3.3 V DAGV 64 DNGV 63 G 3.3 V 9 SCLS GNDA 47 VCCB 62 DARV 66 DNRV 65 3.3 V Analog Vertical R VCCA 50 DARH 52 DNRH 51 3.3 V Analog Horizontal R
3.3 V 3.3 V
DAGH 49 DNGH 48
G
IC Bus to P DATA 3.3 V 3.3 V 3.3 V
DABH 46 DNBH 45
B
4 A 011 5 1 2 3 M24164 3.3 V 8 7 6 2 SCLM 1 SDAM
DABV 61 DNBV 60 GNDB 59 GNDI 53 REFN 54
B
4 A 010 5
16 VIDR REFC 55 17 VIDG To Video 18 VIDB POUT 77 10 VBLK VCCC 70 3.3 V 3.3 V 20 GNDD DACF 69 3.3 V 3.3 V 3.3 V Deflection V 28 SYNV 14 ECLK Filter 24 FILT Filter 25 FLT2 OGAV 58 OGAH 57 +3.3 V 3.3 V 21 OSCL PORA 80 +15 V 3.3 V 3.3 V 3.3 V 23 GNDF PORB 79 +3.3 V 3.3 V 13 REST PORC 78 TBU0 40 -15 V 11 TEST TBU7 33 8 Ports +3.3 V +3.3 V H R V H G V H B V -3.3 V V OPTT 74 MLIN 75 27 SYNH 26 VCCF FREF 68 GNDC 67 OPTI 72 F 3.3 V Analog Focus -3.3 V GNDP 56 Ext. + Int. RESET 3.3 V 3.3 V 3.3 V
H
22 GRES
H
8/83
STV2050A - GENERAL OVERVIEW 1.4 PIN DESCRIPTION AND PINOUT DIAGRAM The following legend applies to the Pin Description Table below:
X = Undefined "0" = Low Level Output HZ = High Impedance "1" = High Level Output Reset Status and Remarks HZ
Table 1. Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name SDAM SCLM GNDQ GNDK VCCQ VCCK SDAO SDAI SCLS VBLK TEST VCCN REST ECLK GNDN VIDR VIDG VIDB VCCD GNDD OSCL GRES GNDF FILT FLT2 VCCF SYNH SYNV GNDJ GNDL VCCJ VCCL TBU7 TBU6 TBU5 TBU4 Description Master Bus: "Data" Master Bus: "Clock" Digital Supply: Ground Digital Supply: Ground Core / RAM Digital Supply: 3.3 V Core / Digital Supply: 3.3 V Slave Bus: "Data" output Slave Bus: "Data" input Slave Bus: "Clock" Video Pattern Blanking Reserved Shield Supply Digital Supply: 3.3 V Reset Reserved Digital Supply: "Ground" Video Pattern Output: "Red" Video Pattern Output: "Green" Video Pattern Output: "Blue" Video Generator Supply: 3.3 V Video Generator Supply: Ground RC for internal oscillator R for internal oscillator PLL Supply: Ground Filter for PLL Filter for PLL Supply PLL: 3.3 V Horizontal Synchronization input Vertical Synchronization input Digital Supply: Ground Digital Supply: Ground Core Digital Supply: 3.3 V Ring / Buffer Digital Supply: 3.3 V IC BUS Expander IC BUS Expander IC BUS Expander IC BUS Expander
"0"
Must be grounded "0" Must be grounded 0 Volts 0 Volts 0 Volts
HZ HZ HZ HZ
X X X X
9/83
STV2050A - GENERAL OVERVIEW
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin Name TBU3 TBU2 TBU1 TBU0 GNDH VCCH GNDG VCCG DNBH DABH GNDA DNGH DAGH VCCA DNRH DARH GNDI REFN REFC GNDP OGAH OGAV GNDB DNBV DABV VCCB DNGV DAGV DNRV DARV GNDC FOCR FOCS VCCC ADS0 OPTI VCCM OPTT MLIN GNDM X X X X Reset Status and Remarks Description IC BUS Expander IC BUS Expander IC BUS Expander IC BUS Expander Analog Supply: Ground D/A Interface Analog Supply: 3.3 V Analog Supply: Ground Analog Supply: 3.3 V Horiz. Convergence Output: Blue, negative Horiz. Convergence Output: Blue, positive Horiz. Convergence Output Supply: Ground Horiz. Convergence Output: Green, negative Horiz. Convergence Output: Green, positive Horiz. Convergence Output Supply: 3.3 V Horiz. Convergence Output: Red, negative Horiz. Convergence Output: Red, positive Floating GND for bandgap filter IREF Loop for H&V Convergence & Focus Filter pin for IREF current IREF GND for Bandgap HZ HZ HZ HZ HZ HZ HZ HZ HZ Horiz. Reference output for electrical loop Vert. Reference output for electrical loop Vert. Convergence Output Supply: Ground Vert. Convergence Output: Blue, negative Vert. Convergence Output: Blue, positive Vert. Convergence Output Supply: 3.3 V Vert. Convergence Output: Green, negative Vert. Convergence Output: Green, positive Vert. Convergence Output: Red, negative Vert. Convergence Output: Red, positive Focus Supply: Ground Focus Reference Output Focus Signal Output Focus Supply IC Slave Bus Address Selection Input for optical sensor support Ring / Inputs Digital Supply: 3.3 V I pin: Latched at measuring line or with sys. clock; O pin: Push/pull, output can be switched to high impedance Measuring Line Signal Output Digital Supply: Ground
HZ HZ HZ HZ HZ HZ HZ Reference Current Code 0(hex) X
Input "0"
10/83
STV2050A - GENERAL OVERVIEW
Pin No. 77 78 79 80 Pin Name POUT PORC PORB PORA HZ Input Reset Status and Remarks Description Protection Pin Control Normally used for electrical loop feedback detection. Can also be set as an inpout or an output.
Figure 5. Pinout Diagram
GNDM MLIN OPTT VCCM PORB PORC POUT FOCR GNDC DARV DNRV
65 64
PORA
VCCC
70
80
75
SDAM SCLM GNDQ GNDK VCCQ VCCK SDAO SDAI SCLS VBLK TEST VCCN REST ECLK GNDN VIDR VIDG VIDB VCCD GNDD OSCL GRES GNDF FILT
FOCS
ADS0
OPTI
1
DAGV DNGV VCCB DABV DNBV GNDB OGAV OGAH GNDP
5
60
10
55
REFC REFN GNDI DARH DNRH VCCA DAGH DNGH GNDA DABH DNBH VCCG GNDG
15
50
20
45
PQFP80
24 25 30 35 40 41
VCCH GNDH
FLT2
GNDJ
SYNV
GNDL VCCJ
VCCL TBU7
TBU6 TBU5
TBU4 TBU3
TBU2 TBU1
VCCF SYNH
TBU0
11/83
STV2050A - STRUCTURE OF THE PROGRAMMING SYSTEM
2 STRUCTURE OF THE PROGRAMMING SYSTEM
2.1 DATA STORAGE The STV2050A is a programmable device. Some of the data, mainly the convergence parameters, must be able to be easily changed during TV set alignment or by the user, and must be memorized when the TV set is switched off in order to be recovered when switched back on. This data must therefore be stored in EEPROM. The STV2050A has an embedded RAM for storing data used "in real time" at a high speed. In order to simplify the microcontroller software, and to ensure a quick startup, the STV2050A directly controls one or more (or up to seven) EEPROMs. The STV2050A has 2 ports for IC connections: - The first one is used only for "SLAVE" connections: it is used to interface with a microcontroller in order to control the IC (customer adjustments,...). The microcontroller can write and read the embedded RAM via this slave port. - The second one is used only for "MASTER" connections: it is used to interface the STV2050A with the EEPROM that stores the convergence data and some user adjustments. The transfer of data between the EEPROM and the embedded RAM is fully managed by the STV2050A. Figure 6. IC BUS Data Transfer
STV2050A
From / To MCU
Slave IC Interface Embedded RAM Logic Core
Data Tranfer Control
Master IC Interface
EEPROM 2k x 8 bits
12/83
STV2050A - STRUCTURE OF THE PROGRAMMING SYSTEM 2.2 OVERVIEW OF EMBEDDED RAM ORGANIZATION The RAM consists of 3 banks: The first one, the "Red and IC Bank", uses 24-bit words. The two other banks, the "Green Bank" and "Blue Bank", both use 22-bit words. Each bank has 208 words with addresses from 00(hex) to CF(hex). These 3 x 208 words are allocated to the "dynamic" convergence parameters. (Refer to Section 4.1 "CONVERGENCE CORRECTION VALUES" on page 18.) The "Red and IC Bank" has 33 additional words: addresses from D0(hex) to EF(hex) and FE(hex). These words are used to buffer the IC Bus registers. As shown in this figure, each word can be pointed to by a sub-address (SA). Thus, each subaddress points to 24- (or 22-, depending on the bank) bit wide words. A word virtually consists of three bytes (24-bits) named D0, D1 and D2 as shown in the following figure. The bit order is named as follows: D0[7] is the MSB and D2[0] is the LSB
MSB D0 Byte Bit 7 6 5 4 3 2 1 0 7 6 5 D1 Byte 4 3 2 1 0 7 6 5 D2 Byte 4 3 2 1 0
LSB
Note: Bit D0[7:6] is not physically implemented in the "Green" and "Blue" banks.
13/83
STV2050A - STRUCTURE OF THE PROGRAMMING SYSTEM Figure 7. Color Banks
BANK:
Red and IC
00
Green
Blue
24 bits
22 bits
22 bits
I2C sub-address (SA)
Dynamic Correction Values for the Red Channel
CF D0
Dynamic Correction Values for the Green Channel
Dynamic Correction Values for the Blue Channel
Protected IC Registers
E2 E3 EF FE
Ajustment Data Set
Non-protected IC Registers
Note: Bits 22 and 23 of the "Red and IC bank" may be used for general purposes. They are stored together with the convergence data in the external EEPROM.
2.3 ADJUSTMENT DATA SETS The set of data stored at addresses D0 to E2 is called an ADS (Adjustment Data Set). The STV2050A can store up to three ADSs in one standard EEPROM. Refer to Section 6 "MASTER IC BUS INTERFACE" on page 28.
14/83
STV2050A - SLAVE IC BUS INTERFACE
3 SLAVE IC BUS INTERFACE
3.1 FEATURES The IC interface is controlled by 4 pins: 3.1.1 ADS0: IC Address and PLL Mode The level at this pin corresponds to bit 1 in the first byte in bus transmissions. - If ADS0 is connected to GND, the analog outputs will be automatically switched on after the reset sequence, and once the internal PLL is activated. - If the pin is connected to VCC, the DACs will remain in high impedance. The internal PLL is inhibited, and the IC must use an external PLL. 3.1.2 SCLS Bus Clock The polarity and timing for this pin comply with IC Bus specifications. 3.1.3 SDAI Bus Data Input The polarity and timing for this pin comply with IC Bus specifications. 3.1.4 SDAO Bus Data Output The polarity reversal and timing for this pin comply with IC Bus specifications. Abbreviations used: S P DA DR DW SA = = = = = = Start condition Stop condition Device address Device address for read Device address for write Sub-address Data bytes
D0, D1,... Dn=
The slave accepts the following DA subaddresses depending on the hardware configuration defined on pin ADS0.
ADS0 0 (grounded, internal PLL only) DR = 39, DW = 38 1 (3.3 Volt, external PLL only) DR = 3B, DW = 3A
For the 00 to CF address range (RAM), an autoincrement function can be enabled using the AIE (Auto Increment Enable) bit in the E7 register.
AIE 0 = Autoincrement disabled 1 = Autoincrement enabled
15/83
STV2050A - SLAVE IC BUS INTERFACE If the autoincrement function is enabled, the internal address is automatically incremented after 3 bytes are either written or read. When the autoincrement counter reaches the CF address, the counter stops counting and any additional data will be written to or read from the CF address. 3.2 COLOR BANK SELECTION As previously mentioned, the embedded RAM is mapped in 3 banks called the "Red and IC Bank", "Green Bank" and the "Blue Bank". A bank is selected using the CBS[1:0] (Color Bank Selection) bits located in the E7 register address.
CBS[1:0] 00 = Red and IC bank selected 01 = Green bank selected 10 = Blue bank selected 11 = Red and IC bank selected
However, sub-addresses D0 to EF and FE (physically mapped in the "Red and IC Bank") are independent of the actual bank selection. 3.3 WRITE COMMANDS Three formats of write commands are supported: - 5-byte write commands to any valid sub-address S DW SA D0 D1 D2 P If the auto-increment function is enabled, the internal address is at SA+1 after the command, otherwise it is still at SA. - 2-byte write commands for defining a sub-address cursor position or for changing the current sub-address without transmitting data. S DW SA P The sub-address is at SA after the command. - Auto-increment write commands for sub-address range 00 to CF If the auto-increment function is enabled, the internal address counter is incremented each time 3 bytes are written: S DW SAi Di0 Di1 Di2 Di+10 Di+11 Di+12... Dn P otherwise every group of 3 bytes is written to SA and the sub-address does not change. S DW SAi Di0 Di1 Di2 Di0 Di1 Di2... ... Dn P When a group of three data bytes within the 00 to E2 address range has been received, the slave will store them in the appropriate embedded RAM location. Only complete groups of three data bytes are stored. IC registers start to be updated when the first data byte is received. Only complete bytes are written. All write commands which do not comply with the formats described above are rejected.
16/83
STV2050A - SLAVE IC BUS INTERFACE 3.4 READ COMMANDS Read commands may access the IC internal RAM as well as all IC registers. Read commands in the 00 to CF range read from the RAM bank that is defined by the two CBS bits that have been previously transmitted to the E7 register by a write command. Addresses in the D0 to E2 range are mapped to the corresponding section of the red color RAM if the RRP bit in the EF register is `0'. Otherwise the corresponding internal register values are transmitted. If the SA is in the 00 to CF address range, the position of the cursor is implicitly defined by the SA. An access to any other SAs will switch off the cursor. It will be switched on again if an address in the 00 to CF range is selected. Three formats of read commands are supported: - Random read commands from any valid IC internal address S DW SA S DR SA D0 D1 D2 P If the auto-increment function is enabled, the internal address is at the SA+1 after the command, otherwise it is still at the SA. - Read commands from the actual internal address S DR SA D0 D1 D2 P If the auto-increment function is enabled, the internal address is at the SA+1 after the command, otherwise it is still at the SA. - Auto-increment read commands from addresses within the 00 to CF address range with random start address. S DW SA S DR SA D0 D1 D2...... Dn P If the auto-increment function is enabled, the internal address counter is incremented after 3 bytes are read, otherwise the SA is always read and the internal address does not change. When the last byte of the CF address has been transmitted, the IC internal auto-increment address counter stops counting and the CF value will be read out again. 3.5 IC I/O LINES Digital filters suppress pulses that are less than 1 or 2 clock pulses at the SDAI and SCLS inputs.
17/83
STV2050A - RAM ALLOCATION
4 RAM ALLOCATION
4.1 CONVERGENCE CORRECTION VALUES The convergence correction values are either dedicated to each correction point of each red/ blue/green channel, or common for all points of each channel. (Refer to Section 9 "CONVERGENCE" on page 45.) The values are grouped into 2 families: - Dynamic correction values - Common correction values 4.1.1 Dynamic Correction Values The dynamic values are stored as described in Section 2.2 "Overview OF EMBEDDED RAM ORGANIZATION" on page 13. For each Red, Green and Blue channel, the following can be stored in the embedded RAM: - 13 horizontal "dynamic" correction values on 10 bits, plus 1 parity bit - Up to 16 vertical "dynamic" correction values on 10 bits, plus 1 parity bit For each correction point there is one corresponding word in the 00(hex) to CF(hex) sub-address range. Bits are stored in the corresponding "Red Bank", "Green Bank" and "Blue Bank" as follows:
MSB BYTE D0 BYTE D1 2 1 0 7 6 5 4 3 2 1 0 7 6 5 BYTE D2 4 3 2 1 0
LSB
Bit
7
6
5
4
3
Horizontal Correction[9:0]
Vertical Correction[9:0]
- Bit D1[3] is the horizontal correction parity bit - Bit D1[2] is the vertical correction parity bit - Bits D1[3:2] are generated by the STV2050A. Their value can be read out only.
Note: The STV2050A automatically checks the parity bits of each convergence value before applying them to the DACs. Refer to Section 14 "SECURITIES" on page 62.
The sub-address corresponds to the coordinates of the point on the screen where the vertical and horizontal lines meet, as shown in the following figure:
18/83
STV2050A - RAM ALLOCATION Figure 8. Addressing a Correction Point
0 1 2 6 15
0 1
Address: 76(hex)
2
VISIBLE SCREEN AREA
7
12
4.1.2 Common Correction Values The common correction values are stored in the "adjustment data sets" of the Red and IC channel. See Figure 7 "Color Banks" on page 14 and Section 9.1 "GLOBAL ADJUSTMENTS - COMMON PARAMETERS" on page 45. 4.2 IC REGISTERS All IC registers are implemented in the "Red and IC Bank" of the embedded RAM. As it can be useful to store some of the IC register content in the EEPROM, the embedded RAM allocation is divided into two parts: - From sub-address D0 to E2 (included), contents can be stored in the EEPROM, and can then be restored, - From sub-addresses E3 to EF and FE, contents are lost when the STV2050A is switched off.
19/83
STV2050A - RAM ALLOCATION 4.2.1 Registers Storable in the EEPROM
MSB
LSB BYTE D0 BYTE D1 2 1 0 7 6 5 4 3 2 1 0 7 6 5 BYTE D2 4 3 2 1 0
SA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2
7
6
5
4
3
RFH[7:0] RFV[7:0] ORH[7:0] ORV[7:0] x PR S PD PD PD CBA 0 AM S[0 x PO PO PO CBA X
GFH[7:0] GFV[7:0] OGH[7:0] OGV[7:0] PL GO HV TSM X X GAV [1:0] X X GAH [1:0] ML E VB VA EE FA ST SA AFS[1:0 ] X X X
BFH[7:0] BFV[7:0] OBH[7:0] OBV[7:0] X X X X X
BGA[4:0] PBV[3:0] HGP[6:0]
PM PM HV HB HA EE TV TV HV ACL[1:0 ] VG VF PP
MLN[8:0] VVB[5:0] BPV[5:0] ASP[2:0] VFP[7:0] FSB[7:0] DCB[7:0] CBH[7:0] CBV[7:0] FS HIF[1:0] O
PBH[3:0] x AC W x
HVB[5:0] BPH[5:0] HRD[5:0] VGD[5:0] VST[7:0] DCT[7:0] CGH[7:0] CGV[7:0]
HGD[5:0] VGP[7:0]
IIE IFA DC T[8]
x
ICV[5:0] HDP[6:0] CRH[7:0] CRV[7:0]
FV1[5:0] OL GL FIN DI EE O RCH[3:0] SRH[7:0] SRV[7:0] DI G x x x
FV2[5:0] NOM[7:0] GCH[3:0] SGH[7:0] SGV[7:0]
FV3[5:0]
FVR[5:0] TOL[7:0] BCH[3:0] SBH[7:0] SBV[7:0] BCV[3:0]
RCV[3:0]
GCV[3:0]
20/83
STV2050A - RAM ALLOCATION 4.2.2 Registers Not Storable in the EEPROM
MSB
LSB BYTE D0 BYTE D1 2 1 0 7 6 5 4 3 2 1 0 7 6 BYTE D2 5 4 3 2 1 0
ADD E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF FE
7
ST L X
6
X
5
X
4
3
GC DH PP CD CD DVLON X PO PO PO CBAX X X X X X X X X
STV2050A code = 30(hex) PL GO HV TSM S09 [3:0] S13[7:0] X X X X X X X GAV [1:0] GAH [1:0]
S0 S1 19
RESERVED
S0 S0 23
PD PD PD CBA
S0 S1 MS EL 19YO S0 S1 S0 S1 1951
X PIC PIB PIA
OP OD OO OD I SSTX X X X X X X X X
S10 [3:0]
S12 [3:0]
S14[7:0] X X X X X X X TE 1
AIE X
CBS [1:0]
MVR[7:0] EEPROMadd [2:0] X X X X X X X X X X X X X X X X X VD C X ADS[1:0 RWM [2:0] ] COV[2:0] GC VH PV X
MVG[7:0] X HAM[3:0] PAS[4:0] S0 S1 19 X X X
MVB[7:0] X STX[3:0]
X
X
X
X
X
X
X
HO1 [5:0] VO1[5:0] HO3[5:0] VO3[5:0] X RU RU RU E12X 0 0 0 0
HG1[3:0] VG1[3:0] HG3[3:0] VG3[3:0] X X X
X X X X
X X X X
HO2[5:0] VO2[5:0] HO4[5:0] VO4[5:0] X X X X X
HG2[3:0] VG2[3:0] HG4[3:0] VG4[3:0] X 0 0
TE TE TE RR 234P 0 0 0 0
X
SS DT EE
0
0
0
0
0
TBU[7:0]
Note: X = Don't care, 0 or 1: The corresponding bit MUST be set to this value for normal operation.
21/83
STV2050A - TIMEBASES
5 TIMEBASES
5.1 LINE LOCKED PLL AND SYSTEM CLOCK A frequency-multiplying PLL derives the internal system clock from the incoming signal at the SYNH pin. This signal is derived from horizontal deflection. Figure 9. Line-Locked PLL and System Clock
STV2050A
SYNH
PLL
System Clock
PRS
100 nF
15 K 10 nF
15 K 10 nF
1.5 nF
The PLL is designed to drive 1H, 2H, HDTV and SVGA applications. Two loop filters can be implemented using the FILT (pin 24) and FLT2 (pin 25) pads. The selection can be forced by the PRS bit in the D5 register.
PRS 0 = FILT selected (2H and above range operation recommended) 1 = FLT2 selected (1H range operation recommended)
The horizontal deflection is often turned off when switching TV set modes. Therefore the PLL provides a base frequency when the external sync signal is missing (both H and V sync signals are missing).
22/83
STV2050A - TIMEBASES The N(clk/line) ratio between the system clock and the incoming sync signal is calculated using the HGD[5:0] and HRD[5:0] values in the D8 register. (Refer to Section 7.2.1 "Horizontal Grid Adjustment" on page 35): N(clk/line) = 14 (HGD+1) + 2 (HRD+1) where: N(clk/line) HGD HRD < > > 512 15 15
For all modes, in normal operation, the incoming timing signal at the SYNH pin will not have a phase deviation greater than 2 s from line to line. Greater phase deviations may occur when switching modes or changing channels. The PLL is expected to recover from these events and lock within one vertical field of consistent phase that is within the normal horizontal operation limits. 5.2 SYNCHRONIZATION INPUTS The two synchronization inputs, SYNH (pin 27) and SYNV (pin 28) slice the Line or the Frame Flyback, respectively, via a Schmitt trigger. This also ensures a very stable detection of the synchronization signals, regardless of the temperature. Figure 10. Synchronisation Signals
Logic Level VD 1
(2)
(1)
Vin 0 Vdown Vup VCC
5.3 HORIZONTAL TIMEBASE The horizontal timing is based on the built-in PLL. 5.3.1 Horizontal DAC Phase In order to compensate the delay of the external amplifiers and the response time of the convergence coils (td ), the values for convergence correction are given out prior to the corresponding horizontal video position. The time delay between video position and the output of
23/83
STV2050A - TIMEBASES the corresponding convergence correction value is defined by the Horizontal DAC phase HDP[6:0] value in the DB register. The following range for the horizontal DAC phase is allowed: 0 HDP 2 x HGD The timing of the DAC output leads the most if HDP is equal to zero. Figure 11. Horizontal DAC Phase
HGN HGRID
n-3 n-2 n-1
n
n+1 n+2 n+3
HGD HGD
coil current
HDP
DAC output
n-2
n-1
n
n+1
n+2
n+3 n+4
5.3.2 Horizontal Width Adjustment In order to fit the video pattern into the full visible area of the screen, the width of the pattern may be adjusted. Horizontal width adjustment is done by changing the number of clock cycles between the vertical grid lines during retrace and the visible grid. The timing for the corresponding DAC values is changed accordingly. Refer to Section 7.2.1 "Horizontal Grid Adjustment" on page 35.
5.3.3 Auto-Calibration of DACs All the DACs of the STV2050A can be automatically calibrated. This feature ensures a high matching stability in both time and temperature. The process involves the sequential calibration of 120 cells. To ensure optimal results, each cell must be calibrated at least every 4 ms. The duration of one cell calibration must be greater than 2us. This duration is controlled by the internal "calibration clock". The calibration clock is generated using a divider of the system clock. (Refer to Section 5.1 "LINE LOCKED PLL AND SYSTEM CLOCK" on page 22). The division ratio is programmable via the ACL[1:0] bits in D8.
24/83
STV2050A - TIMEBASES
ACL[1:0] 00: No calibration 01: Division by 16 10: Division by 32 11: Division by 48
Autocalibration can take place either during the full line, or during the line retrace only. This is controlled by the ACW bit in the D8 register.
ACW 0: During line retrace only 1: During the full line
If the "During Line Retrace Only" autocalibration is selected, the number of DAC cells calibrated during each line retrace is defined by the AFS[1:0] value in the D8 register. AFS[1:0]
00: 1 cell / line 01: 2 cells / line 10: 3 cells / line 11: 4 cells / line
Two autocalibration modes can be selected by the AMS[0] bit in the D5 register.
AMS[0] 0: The autocalibration process is not synchronized to vertical timing 1: The autocalibration is synchronized to vertical IC timing. The counter which selects the DAC cells that are to be calibrated is reset on each frame retrace.
The time interval for auto-calibration is normally centred to the retrace. But it is possible to adjust the start point by programming the ASP[2:0] bits in the D8 register. One step corresponds to one system clock cycle. 5.4 VERTICAL TIME BASE 5.4.1 Vertical Synchronization Signal The vertical timing is based on the vertical deflection signal. A debounce filter is implemented to prevent interference on the SYNV signal caused by crosstalk, mainly from horizontal deflection. This filter accepts a rising edge of the SYNV signal only when SYNV is 'LOW' for a time 8 TV lines (determined by 8 pulses at the SYNH input). Figure 12. Vertical Synchronization Signal
V - deflection
SYNV > 8H VSYNC
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STV2050A - TIMEBASES
5.4.2 Field Parity Recognition In the case of a standard STV2050A implementation, synchronization is achieved using signals extracted horizontally (Line Flyback) and vertically (Frame Flyback). Unfortunately, depending on the components and the configuration, the phase relationship between these signals is not the same in every TV chassis. In this case, field parity recognition can be unreliable unless special features are implemented. The STV2050A can achieve perfect field parity recognition using the "Vertical Sync shifT" (VST). When the VST[7:0] bits in the DA register are set to the optimum value, the STV2050A distinguishes perfectly between the two fields. This is used to control the interpolation of the convergence values and the video pattern generator according to the interlaced scanning scheme. The correct VST value can be evaluated by measuring the timing of the vertical pulse. This timing is measured by the STV2050A, and the results are stored in the S13[7:0] and S14[7:0] bits in the E6 register. In non-interlaced mode, field recognition can be switched off by the IIE bit in the DA register. IIE 5.4.3 Field Counter A 4-bit field counter is implemented for controlling the optical alignment procedure. The counter value is stored in the S12[3:0] bits in the E5 register (read only). This counter will be reset to 0000 at IC power-up and will be incremented after every vertical reset. The counter will overflow from 1111 to 0000. (The counter will not be reset when the E5 register is read.) 5.4.4 Convergence Correction Frame Retrace This is the time interval defined as follows: - Start at grid line number 11 + DCB[7:0] bits in the DB register, - Stop at 2 TV lines after the frame pulse + DCT[8:0] bits in the DB register; where DCB and DCT are the number of TV lines.
0 = Interlace OFF 1 = Interlace ON
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STV2050A - TIMEBASES Figure 13. Vertical Time Base
Vertical Pulse Horizontal Pulses
Vertical Grid Number 11 Vertical Convergence Frame Retrace
1 TV line
Register Update
DCB Lines
DCT Lines
Measurement Line MLN Lines
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STV2050A - MASTER IC BUS INTERFACE
6 MASTER IC BUS INTERFACE
A master IC bus implemented in the STV2050A is used to transfer data between the IC embedded RAM and the external 2K x 8-bit EEPROMs (for example, the 24164 manufactured by ST). The protocol supports up to 7 EEPROM addresses which can be selected using the 3 EEPROMadd[2:0] bits in the E9 register. Master activities are initiated either by an external reset of the STV2050A, or by commands from an external MCU via the Slave IC bus. The following features are implemented in the Master IC Bus interface: - Reset the IC bus to the EEPROM - Read a specified data range from EEPROM to RAM - Write a specified data range from RAM to EEPROM - Check if an EEPROM register is available - Power-on sequence - Security features - Generate status information The organization of data in the embedded RAM is completely different from that in the EEPROM register. Therefore, address transformations are required in both directions. This is carried out by the STV2050A in a way that is fully transparent for the user. The external MCU initiates a master access to the EEPROM by writing a command to the E9 address. This command contains information about the type of access and specifies one of seven EEPROMs (refer to Section 6.6 "DATA TRANSFER BETWEEN RAM AND EEPROM" on page 30). The embedded RAM contains convergence correction data and one adjustment data set (ADS) to control the various modes of the STV2050A. Three ADSs can be stored in the EEPROM. One of these three sets is selected by the two ADS[1:0] bits in the E9 command to be mapped to the register RAM area inside the IC. Any command sent from the MCU to the E9 address while the master is active will be lost. Also, the EEPROM address which is included in this command will not be accepted. Before addressing the E9 register, the MCU should check if the master is active. To do this, the RWM[2:0] bits in the E9 register must be set to "001" (bin). The corresponding status is given on the STX[2] bit. If any error are detected during the transmission of data on the EEPROM IC bus, the transmission is stopped and the corresponding STX[3] bit of the status section of the E9 register is set. Read or Write modes can be selected by setting bit RWM[2] in the E9 register.
RWM[2] 0 = Read mode 1 = Write mode
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STV2050A - MASTER IC BUS INTERFACE 6.1 READ OPERATION MODES Two modes of read sequences are implemented by selecting the RWM[1:0] bits. RWM[1:0]
11 (bin): Read all convergence data and an ADS 10 (bin): Read an ADS only
6.2 WRITE OPERATION MODES Three modes of write sequences are implemented by selecting the RWM[1:0] bits. RWM[1:0]
01 (bin): Write all convergence data and one of the three ADSs 00 (bin): Write only one of the ADSs 10 (bin): Write only the "static" (position offset) values
6.3 POWER-ON SEQUENCE At power-on, the master interface runs a special sequence to build up the convergence correction data and the STV2050A RAM is loaded with data from a user-specified EEPROM. 6.4 SECURITY FEATURE DURING DATA TRANFERS Since access to an EEPROM register is critical with respect to system performance, all EEPROM access commands in the E9 register, together with the corresponding addresses, are protected by the 2-bit, error-detecting Hamming code. If the circuit detects an error, the Master will not initiate an EEPROM access and an error bit will be set in the status register. If any errors are detected during the transmission of data on the IC bus, the transmission is stopped and the corresponding STX[3] bit in the status section of the E9 register is set. 6.5 STATUS INFORMATION Four STX[3:0] bits are available in the status section of the E9 register. These bits continuously reflect the activity and the error status of the master IC bus interface. - STX[3] = TRANSMISSION ERROR This bit is set to low if an error in the transmission of an EEPROM access command was detected. It remains low until the next error-free transmission to register E9 is completed. - STX[2] = EEPROM ACCESS FINISHED This bit is set to low when the master IC-bus interface has completed bus activities. This bit does not display the completion of an EEPROM access. This bit is set high by the master at the start of a new bus sequence or by the slave after reading status register E9. - STX[1] = EEPROM R/W This bit is set to low when the master has initiated an access to the EEPROM. It remains low until the sequence is finished or the sequence is terminated by an access error.
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STV2050A - MASTER IC BUS INTERFACE - STX[0] =EEPROM PROBLEM If A Read or Write sequence has been terminated with an access error, the STX[0] bit is set to low. It is set back to high when the master starts the next R/W sequence. 6.6 DATA TRANSFER BETWEEN RAM AND EEPROM Data is transfered using the following IC BUS sequence after a bit in the E9 register has been read or written: S DW SA D0 D1 D2 P Where: - SA = E9: Selection of the E9 register, EEPROMadd[2:0] is the hardware EEPROM address used by the IC Master, - RWM[2:0] selects the Read or Write mode as previously described, - HAM[2:0]: Hamming code used to protect the D0[7:0] and D1[7:4] data bits. Refer to Section 14.2 "HAMMING ENCODING" on page 62. The total transfer lasts approximately 200 ms if the IC master clock is operating at 70 kHz.
MSB
LSB BYTE D0 BYTE D1 2
X
BYTE D2 1 0 7
X
ADD E9
7
6
5
4
X
3
X
1
0
7
6
5
4
X
3
2
6
X
5
X
4
X
3
2
1
0
EEPROMadd [2:0]
ADS[ 1:0]
RWM [2:0]
HAM[3:0]
STX[3:0]
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STV2050A - MASTER IC BUS INTERFACE 6.7 MASTER CLOCK FREQUENCY The IC Master uses its own timebase with a local oscillator. The frequency is fixed by external filter (R1/C and R2) as shown in Figure 14 "Master IC Clock" on page 31. Typical values are: - R1 - R2 -C = = = 82 k 10 k 33 pF
Figure 14. Master IC Clock
STV2050A
I2C MASTER Time Base
SCL out
R2
R1
C
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STV2050A - VIDEO PATTERN GENERATOR
7 VIDEO PATTERN GENERATOR
The STV2050A provides a built-in video pattern generator for convergence adjustments. The RGB signals are generated by 4-bit DACs with a voltage output. The FBLK signal is used to switch the RGB source inside the TV set. The FBLK is a fixed-voltage output. The video pattern generator delivers five types of video patterns: - Cross-Hatch Grid: Displays the physical locations corresponding to the stored correction values. Refer to Section 7.2 "CROSS-HATCH GRID" on page 35. - Cursor: A crosshair is displayed at the place corresponding to the current addressed memory location. - Border Lines: Used to adjust the convergence at the horizontal and vertical edges of the visible screen area. Refer to Section 7.4 "BORDER LINES" on page 37. - Gain Adjustment Lines: Used to easily adjust the gain of the convergence channels and to optimize interlace mode. - Auto-alignment Pattern: Supports an auto-alignment procedure. The video generator also produces the control signals for the optional optical loop functions. The patterns can be modified using several parameters in the registers of the STV2050A.
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STV2050A - VIDEO PATTERN GENERATOR Figure 15. Auto-alignment Pattern
BORDER LINES
0 1 2 Auto-ali gnment pattern 0 1 2 15
SMALL CURSOR
VISIB LE SCREEN
Programmable distance
12
LARGE CURSOR
Progammable for H zoom effect First t wo grids only
Note: It is not possible to display both cursors simultaneously as shown.
7.1 GENERAL FUNCTIONS 7.1.1 Pattern Selection The color components (RGB) for the video pattern can be separately switched on and off by the COV[2:0] bits in the EA register. If the control bit for one color is set to 0, the corresponding DAC output is switched to 0V.
COV[2] COV[1] COV[0] 0: 1: 0: 1: 0: 1: Red = Off Red = On Green = Off Green = On Blue = Off Blue = On
The type of the pattern is selected by the PAS[4:0] bits in the EA register.
PAS[4] PAS[3] PAS[2] 0: 1: 0: 1: 0: 1: Auto-alignment Pattern Off Auto-alignment Pattern On Small Cursor Large Cursor Cursor Off Cursor On
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STV2050A - VIDEO PATTERN GENERATOR
PAS[1] PAS[0] 0: 1: 0: 1: Grid Off Grid On Border Off Border On
The FBLK output is switched to high voltage when at least one color is activated by the COV bits in the EA register when the STA bit in the D7 register is activated. If no color is selected, the FBLK output is switched to low voltage. For other features of the FBLK pin, refer to Section 8.4 "FAST BLANKING" on page 43. The video signal representing a vertical line (grid, border, cursor) has the shape of a pulse with a width of one system clock cycle.
7.1.2 Pattern Visibility Adjustment Since the bandwidth of the RGB signal path is limited, horizontal and vertical lines may appear on the screen with different brightness levels. To compensate for this effect, it is possible to adjust the brightness values for the horizontal line (PBH[3:0]) bits and the vertical line (PBV[3:0]) bits in the D6 register of the video pattern. The video brightness has 4-bit resolution. The 0(hex) value corresponds to the 0.0 V output from the video DACs. The 1(hex) value corresponds to a typical 0.6 V output. All other steps are equidistant. Figure 16. Pattern Visibility Adjustment
2.3 V Analog output
0.6 V
Digital value 0000 0001 0010 1111
If the PBH bit is set to zero, the amplitude of the auto-alignment pattern is determined by the PBV bit. Using the VDC bit in the EA register, the frequency compensation of the video DACs can be adapted according to the system clock.
VDC 0: Low Current 1: High Current
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STV2050A - VIDEO PATTERN GENERATOR 7.2 CROSS-HATCH GRID The convergence values are adjusted and stored for an array of 16 x 13 points. These points can be displayed by the grid lines of the video generator. The deflection correction at the grid points corresponds to the digitally stored values. Several programming features are used to adapt the grid, and therefore the convergence adjustment, to the needs of the application. All parameters for the grid are included in the data set stored in the internal RAM. 7.2.1 Horizontal Grid Adjustment The horizontal distance of the grid lines is determined by the values of the HGD[5:0] and HRD[5:0] bits in the D8 register. Refer to Figure 17 "Horizontal Grid Adjustment" on page 35. Between each grid line, a minimum of 16 system clock cycles is required for calculating the convergence. (Refer to Section 5.1 "LINE LOCKED PLL AND SYSTEM CLOCK" on page 22). The geometrical distance between two vertical grid lines can be modified by adding clock cycles between the visible grid lines (HGD) or by adding clock cycles during the horizontal retrace (HRD). - HGD: horizontal grid distance during active line. - HRD: horizontal grid distance during line retrace. The left-right position is controlled by the HGP[6:0] bits in the D7 register. Figure 17. Horizontal Grid Adjustment
H-Flyback
HSYNC
Retrace Retrace 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
Grid (HGP=0)
15
0
1
HGP
Grid (HGP>0)
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
Retrace
Retrace
7.2.2 Vertical Grid Adjustment In the same way, the vertical grid adjustment is done using the VGP[8:0] and VGD[5:0] bits in the D9 register.
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STV2050A - VIDEO PATTERN GENERATOR Figure 18. Vertical Grid Adjustment
VGP+2 12
VRES
0 1 2 VGD 3 4 5 6
V-Retrace
visible screen area
If the VGP bit is programmed to 0, the grid starts with the first line following the two lines that are reserved for the register update procedure. The allowed range for the VGP is included between the 0 and 511 video lines. 7.3 CURSOR 7.3.1 Cursor Size The cursor is available in different shapes. The shape is selected by the PAS[3] cursor-type bit in the EA register.
PAS[3] 0: Small Cursor 1: Large Cursor
7.3.2 Cursor Position The position of the cursor is determined by the most recent write command on the IC bus. The embedded RAM addresses of dynamic convergence correction values correspond directly to grid positions on the screen. They represent cursor positions as well. If the CPV (Cursor Position Vertical) value exceeds the 0...C(hex) range, the cursor is not displayed. If a new write address is within the accepted grid range (after having exceeded the range), the cursor pattern is re-displayed (unless the cursor display is turned off).
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STV2050A - VIDEO PATTERN GENERATOR 7.4 BORDER LINES Convergence adjustments at the edges of the screen are more difficult because the grid points which are involved are not visible. Therefore, additional horizontal and vertical border lines are implemented for making adjustments at these positions. 7.4.1 Border Lines: Left / Right The horizontal position of the border lines is programmable by the BPH[5:0] bits in the D7 register.
00h 01h to 1Fh
The position of the border lines is identical to the vertical grid lines at horizontal grid positions 1 and 15 The border lines move toward the centre of the screen in increments of BPH clock cycles. The range for the shift of the border line is one horizontal grid distance.
Figure 19. Border Lines
Grid
15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
BPH
BPH
Borderlines
Note: The BPH bit must be smaller than the HGD bit.
7.4.2 Border Lines: Bottom / Top The vertical position of the border lines depends on bits BPV[5:0] in register D7.
00h 01h to 1Fh The position of the horizontal border lines is identical to the horizontal grid lines at positions 0 and 12. The horizontal border lines move toward the centre of the screen by BPV video lines. The allowed range for the BPV value is one vertical grid distance.
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STV2050A - VIDEO PATTERN GENERATOR Figure 20. Vertical Border Lines
V-Gridlines
11 12 BPV 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 BPV
Border Lines
Note: The value of the BPV bit must be smaller than that of the VGD bit.
7.5 GAIN ADJUSTMENT LINES The "Gain Adjustment Lines" pattern is used mainly for 2 purposes: - To calibrate the convergence currents in order to achieve a consistent geometrical correction on the screens of a series of PTVs, - To have an easy visual adjustment of the interlace mode. The cursor has two different shapes, one for the adjustment of the vertical gain and another for the adjustment of the horizontal gain. The video pattern for the gain cursor is defined in the EA register.
GCP VHV 0: 1: 0: 1: Gain cursor video pattern off Gain cursor video pattern on Horizontal gain cursor video pattern Vertical gain cursor video pattern
7.5.1 Video Pattern for Horizontal Gain Cursor The horizontal gain cursor can be used for adjusting the horizontal convergence channels. The video pattern in the odd field is identical to the video pattern of the large cursor displayed at the centre of the visible grid.
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STV2050A - VIDEO PATTERN GENERATOR Figure 21. Video Pattern for Horizontal Gain Cursor
Vertical Grid Line Number 8 Vertical Grid Line Number 8
Horizontal Grid Line Number 6
Horizontal Grid Line Number 6
Even Field
Odd Field
Note that these controls only modify the video signals. They have no effect on the convergence signals. The dedicated controls of the convergence signals are described in Section 9.7 "MANUFACTURING, AFTER-SALES SERVICE, LAB TRIAL MODES" on page 49. 7.5.2 Video Pattern for Vertical Gain Cursor The video pattern for the vertical gain cursor is identical to video pattern for the horizontal gain cursor (displayed at the centre of the visible grid), except for one horizontal line which is added only in the even TV field. Figure 22. Video Pattern for Vertical Gain Cursor
Vertical Grid Line Number 8 Vertical Grid Line Number 8
Horizontal Grid Line Number 6
Horizontal Grid Line Number 6
Additional Line
Even Field
Odd Field
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STV2050A - VIDEO PATTERN GENERATOR 7.6 AUTO-ALIGNMENT PATTERN The auto-alignment pattern is a rectangular, highlighted part of a screen with a constant brightness (horizontal brightness). See Figure 23 "Auto-alignment Video Pattern" on page 40. The On/Off is controlled by the PAS[4] bit in the EA register
PAS[4] 0: Auto-alignment pattern off 1: Auto-alignment pattern on
The size and the position of the pattern can be controlled by the EB and EC registers. The pattern is defined by its horizontal and vertical start and stop values: HO1, HG1, HO2, HG2, VO1, VG1, VO2 and VG2.
HG1[3:0] HO1[5:0] HG2[3:0] HO2[5:0] VG1[3:0] VO1[5:0] VG2[3:0] VO2[5:0] Grid number of horizontal pattern start Offset of horizontal pattern start (number of clock cycles, 1 grid max.) Grid number of horizontal pattern end Offset of horizontal pattern end (number of clock cycles, 1 grid max.) Grid number of vertical pattern start Offset of vertical pattern start (number of video lines, 1 grid max.) Grid number of vertical pattern end Offset of vertical pattern end (number of video lines, 1 grid max.)
Offset position values must be one grid distance smaller than the vertical grid numbers for start or stop positions. Figure 23. Auto-alignment Video Pattern
Gridline HG1 Gridline HG2
HO2
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VO2
Gridline VG2
HO1
VO1
Gridline VG1
Autoalignment Pattern
STV2050A - VIDEO PATTERN GENERATOR The pattern may be defined so that an end value is less than the start value. In this case, the window will wrap around through the retrace without any interruptions (two or four rectangles will be highlighted on the screen). The auto-alignment pattern signal is influenced by the horizontal or vertical blanking function.
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STV2050A - BLANKING OF VIDEO SIGNALS
8 BLANKING OF VIDEO SIGNALS
The output of the RGB signals can be set to 0V during the horizontal and vertical retrace. The function is controlled by the D6 register. The horizontal and vertical retrace blanking function can be enabled independently. 8.1 HORIZONTAL BLANKING The HBE bit in the D6 register is used to enable/disable the horizontal blanking.
HBE 0: Horizontal Blanking Off 1: Horizontal Blanking On
The start and end edge positions are determined by the HVB[5:0] bits in the D6 register. If the horizontal blanking is enabled, the video outputs are set to 0V from the HVB clock cycles before grid line number 15 until the HVB clock cycles after grid line number 1. The useful range for the HVB is one horizontal grid distance. This function is similar to the border line function. If `0' is programmed, grid lines no. 15 and no. 1 are not blanked. Figure 24. Horizontal Grid Lines
Horizontal Grid Lines
14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
HVB
HVB
HVB
HVB
0V DAC Output
0V DAC Output
Note: If the HVB values are greater than the HGD values, unexpected effects will appear on the screen.
8.2 VERTICAL BLANKING The enable/disable control is the VBE bit in the D6 register.
VBE 0: Vertical Blanking Off 1: Vertical Blanking On
The start and end edge positions are determined using the VVB[5:0] bits in the D6 register. The video blanking function ends when the programmed number of VVB video lines, following vertical grid line no. 0, are finished and the next video line following the end of the DAC retrace mode (DCT) has begun. The VVB range is one vertical grid distance. The function works the same as the border line function. If `0' is programmed, grid lines no. 0 and no. 12 are not blanked. If the values pro-
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STV2050A - BLANKING OF VIDEO SIGNALS grammed for VVB are greater than those of the VGD, unexpected effects will appear on the screen. Figure 25. Vertical Blanking
V-Gridlines
12 VVB 0 V blank stop 1 2 3 4 5 6 7 8 9 10 11 V blank start 12 0 VVB
8.3 BLANKING FOR AUTO-ALIGNMENT PATTERN The blanking for the auto-alignment pattern and for the other video pattern are linked to the same timing which is defined by the HVB and VVB bits as described in the following sections.
HAE VAE 0: 1: 0: 1: Horizontal blanking off Horizontal blanking on Vertical blanking off Vertical blanking on
8.4 FAST BLANKING The FBLK pin is used to provide a fast switching signal that selects the source of the video signal to be displayed on the screen. Features are controlled by the D7 register.
STA 0: FBLK depends on the TVH, TVV and FAS bits (see below) 1: FBLK is forced to 1, if a pattern color is enabled by the COV bits. (Refer to Section 7.1.1 "Pattern Selection" on page 33) Blanking of TV picture in horizontal direction 0: Blanking off 1: Blanking on
TVH
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STV2050A - BLANKING OF VIDEO SIGNALS
TVV FAS Blanking of TV picture in vertical direction 0: Blanking off 1: Blanking on 0: Normal TV picture only 1: The normal TV picture is overlapped by the video pattern
The TVH and TVV bits are designed to be used, for example, in front projection applications. They are used to cut off TV video information at the left and right edges, as well as at the top and the bottom of the projection area that belongs to the overscan region in standard TV sets.
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STV2050A - CONVERGENCE
9 CONVERGENCE
The STV2050A generates convergence values from parameters which are stored in the embedded RAM after having being loaded down from the EEPROM. These parameters can be: - Common for the entire screen area for each color. They are called "common values". They are used for global adjustments, as they have the same effect on all the convergence values of the same color and in the same direction (horizontally or vertically). They are used mainly: - To pre-adjust the geometry and convergence, as well as to reduce the necessary action on each separate point, - To compensate the tolerances of the offset and gain for the external components. - Dedicated to each value of the net of 16 points horizontally by 13 points horizontally. They are called "dynamic values", - Added as an offset frame by frame (interlacing), - Forced to special values in alignment modes or during startup and security modes. Figure 26. Convergence Values Computation Path
Common values
Position Offset (" Static" ) E1 , E2
Gain correction Field offset canceller coarse : E0 D2, D3 fine : D0, D1
Dynamic values
to convergence outputs
Interlace DA Calibration DC, DD Measuring E8
9.1 GLOBAL ADJUSTMENTS - COMMON PARAMETERS Three sets of parameters are available for each red, green and blue channel for each horizontal and vertical direction: - Position offset, - Gain correction, - Offset canceller.
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STV2050A - CONVERGENCE 9.1.1 Position Offset (also called "static") This value is added to each dynamic value of the corresponding channel. It is used to reach an optimal dynamic value range, and to make a first rough correction. E1 Register: Horizontal
SRH[7:0] SGH[7:0] SBH[7:0] Red Channel Green Channel Blue Channel
E2 Register: Vertical
SRV[7:0] SGV[7:0] SBV[7:0] Red Channel Green Channel Blue Channel
The Position offset values are in two's complement. 9.1.2 Gain Correction This gain value is applied to the sum of the dynamic value and the position offset (see Figure 26 "Convergence Values Computation Path" on page 45). It is mainly used for compensating the amplification spread of the external components. (Also refer to Figure 31 "Electrical Loop Block Diagram" on page 55). The gain value is divided into 2 ranges, coarse and fine correction. E0 Register: Coarse
RCH[3:0] RCV[3:0] GCH[3:0] GCV[3:0] BCH[3:0] BCV[3:0] Red horizontal Red vertical Green horizontal Green vertical Blue horizontal Blue vertical
D0 Register: Fine horizontal
RFH[7:0] GFH[7:0] BFH[7:0] Red Channel Green Channel Blue Channel
D1 Register: Fine vertical
RFV[7:0] GFV[7:0] BFV[7:0] Red Channel Green Channel Blue Channel
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STV2050A - CONVERGENCE 9.1.3 Field Offset Canceller This offset value is totalled after the gain correction. Its purpose is mainly to cancel the differential offset between all channels (see refer to Section 11 "ELECTRICAL LOOP" on page 55). D2 Register: Fine horizontal
ORG[7:0] OGH[7:0] OBH[7:0] Red Channel Green Channel Blue Channel
D3 Register: Fine vertical
ORV[7:0] OGV[7:0] OBV[7:0] Red Channel Green Channel Blue Channel
The Field offset values are in two's complement.
Note: During the vertical retrace, the field offset canceller values are the only correction values available on the convergence outputs. Refer to Section 9.6 "NORMAL TV OPERATION MODE" on page 48.
9.2 DYNAMIC VALUES Dynamic values are stored in register addresses 00 to CF in the three red, blue and green banks. For their allocation, refer to Section 4.1 "CONVERGENCE CORRECTION VALUES" on page 18. The dynamic values can be adjusted from -512 to +511
Binary Code -512 0 +512 MSB --> LSB '00 0000 0000' '10 0000 0000' '11 1111 1111'
9.3 INTERLACE The interlace correction value is defined by the ICV[5:0] bits in the DA register. This value is added to each convergence value in the field chosen by the IFA bit in the DA register. The interlace mode is enabled by the IIE bit in the DA register.
IIE 0 = No interlace 1 = Interlace mode
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STV2050A - CONVERGENCE 9.4 CALIBRATION Calibrations can be carried out during manufacturing, or during the normal TV operating mode using the automatic self-alignment procedure via the electrical loop. Refer to Section 11 "ELECTRICAL LOOP" on page 55. 9.5 INTERPOLATION The 10-bit dynamic correction values are expanded by interpolation to 14 precision bits. The interpolation of the correction values stored in the embedded RAM produces correction values for the lines between the grid lines. 9.5.1 Vertical Filter A vertical interpolation is performed by the STV2050A in order to provide a smooth correction transition between the stored points. A complex algorithm is implemented in order to improve the interline geometrical aspect, even when not aligned during chassis production or by the end user. 9.5.2 Horizontal Filter For each of the three convergence correction channels, an interpolation filter is implemented to calculate the correction values between horizontally-adjacent correction values. Different configuration options are programmable using the D8 register.
HIF[1:0] 00: Filter is not active 11: Filter is not active 01: Filter is a 3-tap FIR filter (2 values per grid) 10: Filter is a 5-tap FIR filter (4 values per grid)
FSO
0: Filter is switched off during horizontal retrace 1: Filter is running continuously
The positions of the calculated additional correction values are timed independently for the visible grid and the retrace grids. Since operating the filters will increase the DAC frequency by a factor of 2 and 4 respectively, it may be necessary to switch off the filters during the horizontal retrace if the retrace time is short and the line frequency is high. In this case, the filter input data, coming from the vertical interpolation, will be fed directly to the convergence DACs. In any case, this data is processed by the filters in parallel to avoid any discontinuity when the filters are switched back into the data paths. 9.6 NORMAL TV OPERATION MODE The following bits must remain at logical "1" in the E3 register as defined by the default values during reset: - the CDO bit (refer to Section 9.8 "CONVERGENCE OUTPUTS" on page 51),
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STV2050A - CONVERGENCE - the CDN bit (refer to Section 9.7 "MANUFACTURING, AFTER-SALES SERVICE, LAB TRIAL MODES" on page 49). During normal operation mode, the convergence outputs deliver a signal computed as shown in Figure 26 "Convergence Values Computation Path" on page 45. However, during the convergence frame retrace defined by the DCB and DCT values as described in Section 5.4.4 "Convergence Correction Frame Retrace" on page 26, only the field offset canceller values are output. This is used to reduce the power in the convergence amplifiers. 9.7 MANUFACTURING, AFTER-SALES SERVICE, LAB TRIAL MODES 9.7.1 Output of Field Offset Values This mode is used to output the field offset values defined in the D2 and D3 registers. It is controlled by the CDN bit in the E3 register.
CDN 0: Offset values 1: Normal operation
9.7.2 Gain and Offset Measuring Line This mode is used as a manual control of the measuring line used, for example, in the electrical loop. (Refer to Section 11.1 "PRINCIPLE OF OPERATION" on page 55.) During the gain measuring line: - The dynamic values are replaced for each channel by the CRH[7:0] and CRV[7:0] bits for red, CGH[7:0] and CGV[7:0] bits for green and CBH[7:0] and CBV[7:0] for blue in the DC and DD registers for horizontal and vertical values, respectively, - The polarity of these latter values may be changed using the PMH and PMV bits in the D5 register for horizontal and vertical values, respectively, - The gain value is stored in the E0 register for the coarse value, but the fine values are stored in the MVR[7:0] bits for red, MVG[7:0] bits for green and MVB[7:0] bits for blue in the E8 register. During field offset measuring lines, the value applied to the DACs for each channel are given by MVR[7:0] for red, MVG[7:0] for green, MVB[7:0] for blue in register E8 The manual measuring line mode is enabled using the MLE bit in the D5 register.
MLE 0: Manual measuring line disabled 1: Manual measuring line enabled
This may be programmed when the measuring line is inserted using the MLN[8:0] bits in the D5 register. This signal is made available on pin 75 (MLIN).
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STV2050A - CONVERGENCE The insertion type is selected using the GOS bit in the D4 register.
GOS 0: Field offset canceller 1: Gain compensation
The direction is selected by the HVM bit in the D4 register.
HVM 0 = Vertical 1 = Horizontal
9.7.3 Gain Cursor Mode See Figure 27 "Gain Cursors" on page 51. This mode is normally used in conjunction with the corresponding video pattern. (Refer to Section 7.5 "GAIN ADJUSTMENT LINES" on page 38). The STV2050A can generate a special convergence signal (cursor) controlled by the GCD bit in the E3 register.
GCD 0 = Cursor Off 1 = Cursor On
The cursor action is selected by the DHV bit in the E3 register.
DHV 0 = Horizontal Cursor 1 = Vertical Cursor
During the gain measuring lines: - The dynamic values are replaced for each channel by the CRH[7:0] and CRV[7:0] bits for red, CGH[7:0] and CGV[7:0] bits for green and CBH[7:0] and CBV[7:0] for blue in the DC and DD registers for horizontal and vertical values, respectively. - The polarity of these latter values may be changed using the PMH and PMV bits in the D5 register for horizontal and vertical values, respectively. - The gain value is stored in the E0 register for the coarse value, but the fine values are stored in the MVR[7:0] bits for red, MVG[7:0] bits for green and MVB[7:0] bits for blue in the E8 register. In vertical cursor mode, the resulting values applied to the DACs are first positive, then inverted on the following TV line. In horizontal mode, the values are inverted at each TV line. 9.7.4 Field Offset Cursor Mode See Figure 27 "Gain Cursors" on page 51. This mode is normally used in conjunction with the corresponding video pattern. (Refer to Section 7.5 "GAIN ADJUSTMENT LINES" on page 38.)
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STV2050A - CONVERGENCE The STV2050A can generate a special convergence signal (cursor) controlled by the GCD bit in the E3 register.
GCD 0 = Cursor Off 1 = Cursor On
TThe cursor action is selected by the DHV bit in the E3 register.
DHV 0 = Horizontal Cursor 1 = Vertical Cursor
During field offset measuring lines, the values applied to the DACs for each channel are given by the MVR[7:0] bits for red, MVG[7:0] bits for green and MVB[7:0] bits for blue in the E8 register. In vertical cursor mode, the resulting values applied to the DACs are first positive, then inverted on the following TV line. In horizontal mode, the values are inverted at each TV line. Figure 27. Gain Cursors
Middle of Video Grid
n (Even)
+A -A +A
n+1 n+3 n+5
n'+1 n'+3 (Odd)
n'
n'+2 n'+4
n n+2 n+4
n' (Odd)
-A
n+1 (Even)
(Even)
(Even)
Vertical Gain Adjustment
Horizontal Gain Adjustment
When using this mode, the STV2050A must be correctly set in order to recognize the interlaced field. The IIE bit in the DA register must be set to 1. 9.8 CONVERGENCE OUTPUTS The values of the six convergence channels are converted by 14-bit DACs with a differential current output.
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STV2050A - CONVERGENCE Figure 28. Convergence Channel Structure
Differential Control of Convergence Current Outputs
Convergence Value Compensation
DAxx
+
DNxx
Calibrated sources are used to generate the reference current for all CONVERGENCE and FOCUS DACs. Iref The reference current is defined as -------- . (Refer to Section 13 "CURRENT REFERENCE" on 2 page 61.) The outputs can be disabled using the CDO bit in the E3 register.
CDO 0: High impedance 1: Normal operation.
Notes: 1. The CDO bit is a common control for the convergence AND the focus outputs. 2. The CDN bit must be set to 1 for normal operation. Refer to Section 9.7 "MANUFACTURING, AFTERSALES SERVICE, LAB TRIAL MODES" on page 49.
In order to perform a "soft" start of the convergence to avoid damaging the amplifiers, a "Soft Switch On" of the DACs is carried out digitally by applying a reduced digital gain (reduction by factor 2) for at least 1 field after the DACs have been switched on from high impedance to normal operation (using the CDO bit) or when the DACs have been previously switched to the offset values by the slave bus.
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STV2050A - DYNAMIC FOCUS
10 DYNAMIC FOCUS
10.1 PARABOLA CURVE The focus function delivers a current with 6-bit resolution, which is constant for horizontal lines. In vertical direction, the current has the shape of a second order parabola. The parabola is defined by three points, FV1, FV2 and FV3, whose values correspond to the FV1[5:0], FV2[5:0] and FV3[5:0] values which are stored in the DE register. The position of these last 3 points is a multiple of (VGD+1). See Figure 29 "Focus Parabola" on page 53. The parabola is therefore linked to the value of the Vertical Grid Distance. Figure 29. Focus Parabola
Focus DAC
63
FV3 48 FV1 32 FV1
FVR
16
FV2
0
0 x/2 y x 0
TV lines
VFP+3 x = 12 * (VGD + 1) y = 11 * (VGD + 1) FSB
vertical retrace (VRES)
field n
field n+1
The focus DAC will provide a programmable constant value in the FVR[5:0] bits in the DE register at the bottom of the screen and during vertical retrace. The start of the retrace value is programmable using the FSB[7:0] bits in the DA register as shown above. The position is indicated by the VFP[8:0] bits in the D9 register.
Notes: 1. If VRES becomes active before the number of lines for the FSB have been counted, the parabola will be terminated and replaced by the FVR retrace value. 2. The hardware is not equipped with a safeguard device against DAC range overflow. This may occur if the FV2 bit is near the max. positive or negative value and the parabola is not symmetrical to the FV2 centre value. Also, large values for the FSB have to be taken into account.
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STV2050A - DYNAMIC FOCUS 10.2 FOCUS OUTPUTS The focus output signal is delivered on the FOCS pin. This output is normally used together with a static reference generated on the FOCR pin. This static reference corresponds to the mid-range code value. Figure 30. Focus Outputs
STV2050A
Focus W aveform Generator FO CS
6-bit DAC
+
Focus Reference Level
FOCR
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STV2050A - ELECTRICAL LOOP
11 ELECTRICAL LOOP
11.1 PRINCIPLE OF OPERATION It is possible to multiply convergence values with a digital gain value and add a digital offset value to the convergence values during convergence signal processing (see Figure 26 "Convergence Values Computation Path" on page 45). This can be used to compensate offset current and gain differences of the external convergence amplifiers. However, aging and temperature can cause drifting, and the correction values may have to be adjusted. In order to avoid a manual after-sales re-alignment, the STV2050A can perform an automatic update of the field offset canceller values, as well as for the gain correction values. For this purpose a measuring line in the invisible part of the picture (for example, during the frame retrace procedure) can be used to provide measurement values at convergence outputs. (Refer to Figure 31 "Electrical Loop Block Diagram" on page 55.) Offset current and gain values of the amplifiers are measured with comparators, which are connected to the PORA, PORB, PORC port pins of the IC. The reference values are available on the OGAH and OGAV pins. Figure 31. Electrical Loop Block Diagram
Measuring Line Amplifier Convergence Processing DAC
PORA PORB PORC
Yoke
Electrical Loop
OGAH,OGAV
SenseResistor
Once the measurement is carried out, the convenient field offset canceller and gain compensation corrections for the convergence values can be controlled by either an embedded process ("internal loop"), or by an external MCU, when the internal loop is disabled. The loop is activated using the STL bit in the E3 register.
STL 0 = Internal Loop enabled 1 = Internal Loop disabled
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STV2050A - ELECTRICAL LOOP A measuring line is inserted in each frame for measuring either the offset or the gain of the amplifiers. Therefore, the compensation procedure has to run through the offset/gain measurement and horizontal/vertical channels sequentially. The right comparator is activated by the timing of the signals on the OGAV and OGAH pins. (Refer to Figure "" on page 8). Programming is possible when the measuring line is inserted using the MLN[8:0] bits in the D5 register. 11.2 LOOP PARAMETER REGISTER Parameters for the internal loop circuit are defined in the DF register. Offset and gain compensation can be enabled separately using the OLE and GLE bits.
OLE GLE 0 = Offset Loop activated 1 = Offset Loop disabled 0 = Gain Loop activated 1 = Gail Loop disabled
If the FIN bit in the DF register is `high', the device only carries out one single measurement during the first time that the compensation is carried out.
FIN 0: No exception for first loop cycle 1: First loop cycle with fixed parameters for fast operation
The comparison sign of the PORA, PORB and PORC pins can be programmed by using the DIO bit for the offset and the DIG bit for the gain in the DF register.
DIG 0: The level on the port is `high' if the convergence current is too high 1: The level on the port is `low' if the convergence current is too high.
The number of measurements that are evaluated for selecting a new compensation value is determined by the NOM[7:0] bits in the DF register. Number of deviating results among the NOM measurements that do not lead to a change of the actual compensation value is determined by the TOL[7:0] bits in the DF register. 11.3 LOOP STATUS REGISTER All functions for the port control and the gain range control that are influenced by the compensation loop are available via the IC E4 register. This register is used if the gain and/or offset loop is handled by an external MCU. The IC internal loop has its own registers which are mapped to the E4 address in the event of read access to this address. - The PIA, PIB and PIC bits indicate the status of the PORA, PORB and PORC ports respectively. - The ELO bit indicates if the electrical loop is ready (=1) or not (=0).
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STV2050A - ELECTRICAL LOOP 11.4 OPERATION OF THE ELECTRICAL LOOP The electrical loop is started by the STV2050A reset procedure following the readout of the EEPROM and the updating of the IC registers once the convergence outputs are enabled (the S02 and S03 bits in the E3 register are set to 1). If loop operation is enabled with the OLE and GLE bits, the loop sets the RU1 and RU2 bits to Low in the EF register which disables the RAM updating the D0*...D3* and E4 registers. The ELO bit in the E4 register is set to High by the IC reset, which indicates to external MCUs that the first offset/gain compensation is not yet completed. If enabled, the offset and the gain compensation procedures are repeated endlessly. If the offset compensation is enabled by the OLE bit, the measuring line is switched to offset mode (GOS = 0) and the compensation procedure is done sequentially for horizontal (HVM=1) and vertical (HVM=0) channels. If the gain compensation is enabled by the GLE bit, the measuring line is switched to gain mode (GOS=1) and the compensation procedure is carried out for horizontal (HVM=1) and vertical (HVM=0) channels. When the compensation for all channels is completed for the first time, the ELO bit is set to Low in order to supply this information to external MCUs. The activity of the internal loop circuit has to be interrupted if the convergence DACs are disabled (which can be detected at the S02 and S03 bits) or if the STL bit in the E3 register is High or if the GLE and the OLE bits are Low. 11.5 OUTPUT/INPUT PADS 5 pins are dedicated for the electrical loop: PORA, PORB, PORC, OGAH and OGAV. However, these pins can be used for other purposes and are all programmable. 11.5.1 PORA, PORB and PORC Pins These pins can be set as either input or output pins using the corresponding PDA, PDB and PDC bits in the E4 register.
PDA, PDB or PDC 0 = Input 1 = Output
If the ports are set as an input, the value on the port is sampled with the timing set by the PLT bit in the E4 register.
PLT 0: by the system clock 1: at the end of the measuring line
If the ports are set as an output, the value on the port is given by the value of the POA, POB or POC bits in the E4 register.
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STV2050A - ELECTRICAL LOOP 11.5.2 OGAH and OGAV Pins The OGAH (pin 57) and OGAV (pin 58) pins are multi-level output pins. In addition to the normal digital output function (logical "0" and "1"), they can drive a very stable current and can be switched to high impedance. The stable current and the high impedance can be used to generate the reference voltage across a grounded resistor for the gain and offset detection comparators. Each pad is controlled by two corresponding bits in the E4 register.
GAH[1:0] 0 0 = High impedance 0 1 = "0" 1 0 = Iref 1 1 = "1" 0 0 = High impedance 0 1 = "0" 1 0 = Iref 1 1 = "1"
GAV[1:0]
Figure 32. E4 Register
GAV control bit 1 GAV control bit 2
2
GAH control bit 1 GAH control bit 2
OGAV
OGAH
Attention: The OGAV and OGAH pins cannot both drive IREF at the same time.
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STV2050A - OPTICAL LOOP
12 OPTICAL LOOP
12.1 PRINCIPAL OF OPERATION Figure 33. Optical Loop
STV2050A STV 2050D
RGB
Dynamic Gain Static Offset OPTT H V
H/V grid timing
IC P
OPTI
sensor
The STV2050A can deliver a dedicated video pattern known as an "auto-alignment pattern". This pattern is rectangular-shaped, and its width, height and brightness are programmable. Refer to Section 7.6 "Auto-alignment Pattern" on page 40. The presence or absence of this pattern can be detected by optical sensors; for example, by a camera in the production line, or photo detector diodes placed around the Projection screen. The STV2050A can read the status of the sensors within a programmable time limit. The results are made available in the E5 register, allowing the MCU to run a routine for making the necessary corrections. Two pins are dedicated to the optical loop: - The OPPT pin is a port normally used as an output, and can deliver a logical electrical signal with a programmable time limit. - The OPTI pin is an input port for logical 0 or 1 levels. This port is sampled by the STV2050A to indicate the status of the sensor. 12.2 OPTT SENSOR PORT CONTROL The OPTT sensor port can be programmed as an input or as an output by the ODS in the E5 register.
ODS 0 = OPTT is an input 1 = OPTT is an output
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STV2050A - OPTICAL LOOP 12.2.1 OPTT Pin used as an Input The status of OPTT is available in S05 in register E5.
S05 0: < 0.7 V on OPTT 1: > 2.6 V on OPTT
12.2.2 OPTT Pin used as an Output The OPTT output can either be forced to the electrical "1" level, or can be programmed in the same way as the auto-alignment pattern. This is carried out by the OOS bit in the E5 register.
OOS 0: Data output = the ODT bit in the E5 register 1: Programmable timing
In the latter case, the timing of the OPPT signal typically overlaps the auto-alignment pattern. The final signal is used to control the OPTI and OPTT port functions. The timing for the signal is defined by the ED and EE registers. HG3 HO3 HG4 HO4 VG3 VO3 VG4 VO4 Grid number of horizontal start Offset of horizontal start (number of clock cycles, 1 grid max.) Grid number of horizontal end Offset of horizontal end (number of clock cycles, 1 grid max.) Grid number of vertical start Offset of vertical start (number of video lines, 1 grid max.) Grid number of vertical end Offset of vertical end (number of video lines, 1 grid max.)
Offset values larger than one grid distance or invalid vertical grid numbers for start or stop position will cause unexpected results at the OPTT_PATTERN signal. The OPTT_PATTERN signal is not influenced by the horizontal or vertical blanking function. 12.3 OPTI SENSOR STATUS PORT The level applied to the OPTI pin can be read using the S11 bit in the E5 register. The OPTI level can be ANDed with the window defined on the OPTT using the OPI in the E5 register.
OPI 0: S11 = OPTI AND window 1: No windowing
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STV2050A - CURRENT REFERENCE
13 CURRENT REFERENCE
The STV2050A delivers accurate and stabilized currents used to drive the convergence and focus functions. It has an embedded voltage reference (band gap), which is used to generate a reference current (IrefN) The nominal voltage on the REFN pin is 500 mV. The Irefn current must be adjusted to 500 uA. This is obtained by using a temperature stable external resistor of 1 k. The reference voltage may be adjusted by using the BGA[4:0] bits in the D5 register. Figure 34. Current and Voltage References
STV2050A
BGA[4:0] IREFN
Band gap voltage reference
REFN
+
VREFN
REFC
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STV2050A - SECURITIES
14 SECURITIES
14.1 OVERVIEW The STV2050A can prevent overcurrents in the convergence coils, or poor programming, using the following controls: - At power-on reset, or after a reset, all analog outputs are disabled, and the STV2050A waits until at least 2 pulses of each horizontal and vertical signals are received. - As long as the internal set-up is not achieved, the outputs remain disabled. The setup duration is typically 2 field periods. - When setup is achieved, the DAC outputs are not fully released and the values are reduced 50% during one field. - The transfer between EEPROM and embedded RAM of the data stored in register E9 is protected by a Hamming code. - During normal operating mode, each convergence value stored in the embedded RAM is checked by a parity checker before it is applied to the DACs. If a parity error occurs, the S19 bit in the E3, E4, E5 and E9 resisters are set as follows.
S19 0: Parity OK 1: Parity error
An error flag is available in read mode through the slave IC BUS. 14.2 HAMMING ENCODING The E9 register contains certain values which are protected by a Hamming code: :EEPROMadd[2:0], ADS[1:0] and RWM[2:0]. The Hamming code is stored in the HAM[3:0] bits in the E9 register.
MSB
LSB D0 BYTE D1 BYTE 1 0 7 6 5 4
X
D2 BYTE 1 0 7
X
ADD E9
7
6
5
4
X
3
X
2
X
3
2
6
X
5
X
4
X
3
X
2
X
1
X
0
X
EEPROMadd [2:0]
ADS[ 1:0]
RWM [2:0]
HAM[3:0]
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STV2050A - BOOT SEQUENCE To initiate access to an EEPROM, the MCU must generate this code. A simple method is to store the values in a single temporary byte TMP[7:0] and to compute each bit of the Hamming HAM[3:0] bits as follows:
MSB
LSB TMP BYTE
7
6
5
4
3
2
1
RWM [2:0]
0
EEPROMadd [2:0]
ADS[1:0]
HAM[0] = TMP[4] XOR TMP[3] XOR TMP[2] XOR TMP[1] XOR TMP[0] HAM[1] = TMP[6] XOR TMP[5] XOR TMP[4] XOR TMP[2] XOR TMP[0] HAM[2] = TMP[7] XOR TMP[5] XOR TMP[2] XOR TMP[1] HAM[3] = TMP[7] XOR TMP[6] XOR TMP[4] XOR TMP[3] 14.3 SECURITY OUTPUT The POUT output can be considered as an open drain from a functional point of view, that is to say that it can have two electrical states: high impedance or pull-down to the ground. It can be used, for example, to force all external amplifiers to a secured biasing. Refer to Figure "" on page 8. The electrical status of this output is controlled by the PPL bit in the E3 register.
PPL 0: Normal operation 1: High impedance
During normal operation it is pulled down to ground: - if the STV2050A detects a malfunction such as a parity check error or power on reset error. - until the power-on reset is released. Otherwise, POUT is set to high impedance. In this case, the logical status of the POUT pin can be read using the S02 bit in the E3 register.
15 BOOT SEQUENCE
At startup, or following a reset on pin 13, the STV2050A will: - Immediately disable all the outputs (forced to the "zero current" value, in order to protect the application against over-currents in the coils for example),
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STV2050A - IC STATUS REGISTERS - Wait until the HSYNC and VSYNC signals are available on pins 27 and 28 respectively. (At least 2 VSYNC pulses are required). If one signal is missing, the STV2050A remains in Stand-by mode. - Use the IC master to read the EEPROMadd[2:0] data bits in the EEPROM having the hardware address 010 (bin). The EEPROMadd[2:0] bits represent the address of the EEPROM which will be used to setup the STV2050A during the boot sequence,
Note: This is particularly suitable when it is necessary to recover the last configuration used before switching off for example.
- Use the IC master to download all convergence data and registers (from the selected EEPROM, as explained before), - Wait for up to 2 fields after all the data has been downloaded and enable the outputs.
16 IC STATUS REGISTERS
Some registers of the STV2050A can be read via the IC slave bus in order to indicate the updated status of the IC. The update is enabled using the RUE bit in the EF register.
RUE 0: No update 1: Update enabled
The update timing of registers D0 to D3 is determined by the RU1 bit in the EF register.
RU1 0: No update 1: Update after vertical reset
The update timing of the E4 register is determined by the RU2 bit in the EF register.
RU2 0: No update 1: Update after vertical reset
The S01 bit in the E3 or E4 or E5 or E9 registers: - Power-on reset status
S01 0: Reset successfully achieved 1: Reset ongoing
The S02 bit in the E3 register: - Security output (POUT) status
S02 0: "0" (pull down to ground) 1: High impedance
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STV2050A - BUS EXPANDER
17 BUS EXPANDER
The 8 digital outputs (TBU0 to TBU7) can be used as a bus expander (output only) if DTE register EF is set to "1". Each output can be set to logical "0" or "1" using the corresponding TBU[7:0] bits in the FE register.
18 ABSOLUTE MAXIMUM RATINGS
Symbol
VDDMAX TAMB TSTORE Ambient temperature operating range Storage temperature range 10 -25
Parameter
Min.
Typ.
Max.
3.6 70 125
Unit
V C C
19 RECOMMANDED OPERATING CONDITIONS
Symbol VDD PTOT Parameter Power supply voltage Power dissipation Min. 3.0 Typ. 3.3 Max. 3.6 450 Unit V mW
20 ELECTRICAL CHARACTERISTICS
TA= 25 C, unless otherwise specified. VDD = 3.3 V, external components as shown in Figure 4 "Application Circuit" on page 8. 20.1 GENERAL
Parameter Average current on Min. Typ. 100 Max. Unit mA Conditions
20.2 CURRENT REFERENCE
Parameter Adjustable voltage range Temperature drift (10C to 70C) Min. 0.55 45 Typ. Max. 0.45 Unit V V |PPM / C Conditions BGA[4:0] = 00 (hex) BGA[4:0] = 1F (hex)
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STV2050A - ELECTRICAL CHARACTERISTICS 20.3 VIDEO PATTERN OUTPUTS 20.3.1 DACs for RGB
Parameter Resolution Min. Typ. 4 70 Output voltage 0.4 1.9 DNL INL 0.6 2.3 0.1 0.2 Max. 200 0.8 2.7 0.25 0.5 Unit bit mV V V LSB LSB Conditions Code 0000b applied, IOUT < 0.1 mA Code 0001b applied, IOUT < 0.1 mA Code 1111b applied, IOUT < 0.5 mA Except code 0000b Except code 0000b Max. code applied; Ref signal for 10% is the channel of RGB with the max signal value From code 0(hex) to F(hex) From code F(hex) to 0(hex)
Matching between DACs
3
10
%
Rise time (10...90%) Fall time (10...90%) Delay between video DACs (50%)
5 2 4
20 10
ns ns ns
20.3.2 FBLK Output
Parameter Output voltage low Output voltage high Rise/Fall time (10...90%) Min. 2.4 10 Typ. Max. 0.4 Unit V V ns Conditions 2 mA input 2 mA output 15 pF load
20.4 FOCUS DACs 20.4.1 Focus Reference
Symbol IFOCRFOCR Parameter Focus reference current on pin FOCR Temperature drift of output current Min -7 Typ Max. +7 Unit % |PPM / C 0C to 70C Conditions
3 -- Irefn 4
150
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STV2050A - ELECTRICAL CHARACTERISTICS 20.4.2 Focus Signal
Symbol Parameter Highest output current on pin FOCS Smallest output current on pin FOCS Output current matching on pin FOCS versus FOCR Focus DAC DNL (FOCS pin) Focus DAC INL (FOCS pin) Operating range Voltage Rise/Fall time (10...90%) Min -7 Typ Max. +15 5 +5 0.2 0.2 0.7 1 1.5 2 Unit % A % LSB LSB V ms 1.33 k, 15 pF load Conditions Max. code (3F hex) applied, VOUT = 0.5 V Min. code (00 hex) applied Mid-code (20 hex) applied, VOUT = 0.5 V
3 -- IrefN 2
0.5
-5
20.5 CONVERGENCE DACS
Parameter Resolution Max. output current Min. output current Operating range DNL INL Autocalibration adjustment refresh interval Horizontal line frequency Horizontal line retrace time Internal parasitic capacitance on each DAC output Signal / Noise ratio Temperature drift of full scale output current Min. -0.5 0 Typ. 14 2. IrefN 100 1 2 Max. +0.5 1 500 2 4 5 15 TBD 50 12 15 90 35 60 Unit bit % lsb mV LSB LSB ms kHz s pF 300 Hz to 500 kHz, df = 1 kHz Max. code (3FFF) | ppm / Including bandgap temperature xC | drift dB Conditions Max. code applied Code 00h applied Max. VOUT = 100 mV Max. VOUT = 100 mV
20.6 PLL
Parameter Number of System Clock pulses per line Min. 250 Typ. Max. 512 Unit Conditions
20.7 MASTER IC TIME BASE
Parameter SCL Frequency Min. 65 Typ. Max. 85 Unit kHz Conditions Recommended filter
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STV2050A - ELECTRICAL CHARACTERISTICS 20.8 HORIZONTAL AND VERTICAL SYNCHRONIZATION INPUTS
Parameter Threshold V UP Threshold difference V DOWN VUP Temperature drift of V UP Min. 1.4 Typ. Max. 1.8 Unit V V 90 mV Const. supply voltage Ambient temp. 10x70xC Conditions
0.130
20.9 TBU OUTPUTS
Parameter Output voltage at low level (logical "0") Output voltage at high level (logical "1") Min. Typ. Max. 0.4 2.4 Unit V V Conditions 2 mA input current 2 mA output current
20.10 ELECTRICAL LOOP PADS
Parameter Output voltage at low level (logical "0") Output voltage at high level (logical "1") Leakage current at high impedance Output current (GAH = 10 bin.) Temperature drift of Ref current Input logical "0" Input logical "1" 2.6 Min. Typ. Max. 0.4 2.4 1 -0.5 Irefn +0.5 60 0.7 Unit V V A % ppm /xC V V Conditions 2 mA input current 2 mA output current 0 < VOUT < VDD 2 k load, Max voltage = 1V 2 k load, including the temperature drift of the bandgap
Notes: 1. PORA..C Input level can be latched in measuring line or with sys. clock. 2. PORA..C and OPTT input have digital inputs. 3. OPTI is only an input pin. 4. MLIN is only an output pin. It sends a pulse during the measuring line(M_Line, see `gain range control'). The signal can be used to gate the comparators at the PORT A...C pins or to switch time constants.
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STV2050A - PACKAGE MECHANICAL DATA
21 PACKAGE MECHANICAL DATA
Figure 1. 80-Pin Plastic Quad Flat Package
0.10mm .004 seating plane
PQFP080
Dim A A1 A2 B C D D1 D3 E E1 E3 e K L L1 N
mm Min 0.25 2.55 0.30 0.13 22.95 19.90 16.95 13.90 23.20 20.00 18.40 17.20 14.00 12.00 0.80 0 0.65 0.80 1.60 Number of Pins 80 ND 24 7 0.95 0.026 17.45 14.10 0.667 0.547 2.80 3.05 0.45 0.23 23.45 20.10 Typ Max 3.40 0.010 0.100 0.012 0.005 0.904 0.783 Min
inches Typ Max 0.134 0.110 0.120 0.018 0.009 0.913 0.787 0.724 0.677 0.551 0.472 0.031 0.031 0.063 NE 16 0.037 0.687 0.555 0.923 0.791
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STV2050A - ELECTRICAL PIN CONFIGURATION
22 ELECTRICAL PIN CONFIGURATION
Pin 19 26 42 44 50 62 70
Name VCCD VCCF VCCH VCCG VCCA VCCB VCCC GND
Pin 41 47 67
Name GNDH GNDA GNDC VDD
Pin 8 9 11 13 27 28 71 72
Name VDD SDAI SCLS TEST REST SYNH SYNV ADS0 OPTI GND GND VDD
Pin 7
Name SDAO VDD VDD
GND GND
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STV2050A - ELECTRICAL PIN CONFIGURATION
Pin 54 Name REFN Pad Pin 57 58 Name OGAH OGAV VDD Pad VDD GND
GND
Pin 1 2 10 33 34 35 36 37 38 39 40 74 75 78 79 80
Name SDAM VDD SCLM VBLK TBU0 TBU1 TBU2 TBU3 TBU4 TBU5 TBU6 TBU7 OPTT MLIN PORC PORB PORA GND GND GND VDD VDD
Pin 3 15 30
Name GNDQ GNDN GNDL VDD VDD
Pin 5 6 12
Name VCCQ VCCK VCCN
GND
GND
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STV2050A - ELECTRICAL PIN CONFIGURATION
Pin 31 32 73 Name VCCJ VCCL VCCM VDDE Pin 4 20 29 59 76 GND Name GNDK GNDD VDD GNDJ GNDB GNDM GND
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STV2050A - IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION
23 IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION
A
ACL ACW ADS AFS AIE AMS ASP Auto Calibration system cLock............................................................................D8 Auto Calibration Window.....................................................................................D8 Adjustment Data Set ...........................................................................................E9 Number of calibrated cells per line......................................................................D8 AutoIncrement Enable.........................................................................................E7 Autocalibration Mode Selection...........................................................................D5 Autocalibration Start Position ..............................................................................D8
B
BCH BCV BFH BFV BGA BPH BPV Coarse gain of Blue Horinzontal .........................................................................E0 Coarse gain of Blue Vertical................................................................................E0 Blue Fine gain correction Horizontal ...................................................................D0 Blue Fine gain correction Vertical .......................................................................D1 BandGap Adjustment ..........................................................................................D5 Border Position Horizontal ..................................................................................D7 Border Position Vertical.......................................................................................D7
C
CBH CBS CBV CDN CDO CGH CGV COV CPV CRH CRV Calibration value Blue Horizontal ....................................................................... DC Color Bank Selection...........................................................................................E7 Calibration value Blue Vertical ........................................................................... DD Offset values on convergence.............................................................................E3 Convergence and focus output disable...............................................................E3 Calibration value Green Horizontal .................................................................... DC Calibration value Green Vertical ........................................................................ DD Color selection of Video pattern ......................................................................... EA Cursor Position Vertical Calibration value for Red Horizontal .................................................................. DC Calibration value for Red Vertical....................................................................... DD
D
DCB DCT DHV DIG DIO DAC Count Bottom............................................................................................. DB DAC Count Top.................................................................................................. DB Horizontal or Vertical cursor selection.................................................................E3 Sign of gain comparison..................................................................................... DF Sign of offser comparison .................................................................................. DF
E
ELO ............................................................................................................................E4
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STV2050A - IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION EEPROM addEEPROM address ..................................................................................E9
F
FAS FIN FSB FSO FV1 FV2 FV3 FVR FASt blanking enable ..........................................................................................D7 Fast compensation of electrical loop.................................................................. DF Focus Stop Bottom............................................................................................. DA Filter Switched Off during horizontal retrace .......................................................D8 Focus parabola top value................................................................................... DE Focus parabola middle value ............................................................................. DE Focus parabola bottom value............................................................................. DE Focus value during frame retrace ...................................................................... DE
G
GAH GAU GAV GAX GAY GCD GCH GCP GCV GFH GFV GLE GOS OGAH pin configutation ......................................................................................E4 ............................................................................................................................D4 OGAV pin configutation................................................................................. D4,E4 ............................................................................................................................D4 ............................................................................................................................D4 Measurement Cursor on DACs ON/OFF ............................................................E3 Coarse gain of Green Horinzontal.......................................................................E0 Gain Video Pattern enable ................................................................................. EA Coarse gain of Green Vertical.............................................................................E0 Green Fine gain correction Horizontal ................................................................D0 Green Fine gain correction Vertical.....................................................................D1 Gain Loop Enable .............................................................................................. DF Gain or Offset measurement Selection ......................................................... D4,E4
H
HAE HAM HBE HDP HG1 HG2 HG3 HG4 HGD HGP HIF HO1 HO2 HO3 HO4 Horinzontal Autoaligment blanking Enable .........................................................D6 Hamming code ....................................................................................................E9 Horizontal Blanking Enable .................................................................................D6 Horizontal DAC Phase ....................................................................................... DB Horizontal aligment pattern start ........................................................................ EB Horizontal aligment pattern end ......................................................................... EB Start of horizontal optical output......................................................................... ED End of horizontal optical output.......................................................................... ED Horizontal Grid Distance .....................................................................................D8 Horizontal Grid Position ......................................................................................D7 Horinzontal Filter mode .......................................................................................D8 Horizontal aligment pattern start Offset.............................................................. EB Horizontal aligment pattern end Offset............................................................... EB Offset start of horizontal optical output............................................................... ED Offset end of horizontal optical output................................................................ ED
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STV2050A - IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION HRD Horizontal Retrace Distance ...............................................................................D8 HVB Horinzontal Video Blanking position....................................................................D6 HVM Horintal or Vertical Measurement.................................................................. D4,E4
I
ICV IFA IIE Interlace Correction Value.................................................................................. DA Interlace Field choice ......................................................................................... DA Interlace enable.................................................................................................. DA
M
MLE MLN MSY MVB MVG MVR Manual Measuring Line Enable...........................................................................D5 Measuring Line Number......................................................................................D5 ............................................................................................................................E4 Measuring Value for blue channel.......................................................................E8 Measuring Value for green channel ....................................................................E8 Measuring Value for red channel ........................................................................E8
N
NOM Number of measurements.................................................................................. DF
O
OBH OBV ODS ODT OGH OGV OLE OOS OPI ORH ORV Offset canceller Blue Horizontal..........................................................................D2 Offset canceller Blue Vertical ..............................................................................D3 OPTT port direction selection..............................................................................E5 OPTT output data................................................................................................E5 Offset canceller Green Horizontal .......................................................................D2 Offset canceller Green Vertical ...........................................................................D3 Offset Loop Enable ............................................................................................ DF OPTT output mode..............................................................................................E5 OPTI windowing ..................................................................................................E5 Offset canceller Red Horizontal ..........................................................................D2 Offset canceller Red Vertical...............................................................................D3
P
PAS PBH PBV PDA PDB PDC PIA PIB Pattern Selection................................................................................................ EA Pattern Brightness Horizontal .............................................................................D6 Pattern Brightness Vertical..................................................................................D6 Port A Direction Selection ............................................................................. D4,E4 Port B Direction Selection ............................................................................. D4,E4 Port C Direction Selection ............................................................................. D4,E4 Status of the port PORA......................................................................................E4 Status of the port PORB......................................................................................E4
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STV2050A - IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION PIC PLT PMH PMV POA POB POC PPL PRS Status of the port PORC .....................................................................................E4 Port latch timing ............................................................................................ D4,E4 Parity of register DC values ................................................................................D5 Parity of register DD values ................................................................................D5 Port A output data ......................................................................................... D4,E4 Port B output data ......................................................................................... D4,E4 Port C output data ......................................................................................... D4,E4 Security output enable ........................................................................................E3 PLL time constant Selection................................................................................D5
R
RCH Coarse gain of Red Horizontal ............................................................................E0 RCV Coarse gain of Red Vertical ................................................................................E0 RFH Red Fine gain correction Horizontal....................................................................D0 RFV Red Fine gain correction Vertical ........................................................................D1 RRP Register Read Pointer.........................................................................................EF RUE Register Update Enable ......................................................................................EF RU1 D0 D3 registers update timing.............................................................................EF RU2 E4 register update timing ....................................................................................EF RWM Read Write mode for EEPROM ..........................................................................E9
S
S01 S02 S03 S05 S09 S10 S11 S12 S13 S14 S19 SBH SBV SGH SGV SRH SRV SSE STA STL STX Power on reset Status.........................................................................E3,E4,E5,E9 POUT Status .......................................................................................................E3 ............................................................................................................................E3 Status of the OPTT port ......................................................................................E5 Read out the horizontal position..........................................................................E5 Read out the vertical position..............................................................................E5 Status of the OPTI port .......................................................................................E5 ............................................................................................................................E5 1st field vertical pulse timing ...............................................................................E6 2nd field vertical pulse timing ..............................................................................E6 Status : parity check............................................................................E3,E4,E5,E9 Position offset of Blue Horinzontal ......................................................................E1 Position offset of Blue Vertical ............................................................................E2 Position offset of Green Horinzontal ...................................................................E1 Position offset of Green Vertical..........................................................................E2 Position offset of Red Horinzontal.......................................................................E1 Position offset of Red Vertical .............................................................................E2 Soft Switch Enable ..............................................................................................FE Force the video pattern fast blanking ..................................................................D7 ............................................................................................................................E3 Status of Transmission with EEPROM................................................................E9
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STV2050A - IC BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION
T
TBU TE1 TE2 TE3 BUS expander.....................................................................................................FE ............................................................................................................................E7 ............................................................................................................................EF ............................................................................................................................EF
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STV2050A - INDEX OF IC BUS REGISTERS
24 INDEX OF IC BUS REGISTERS
A
ACL .............................................................................................................................................19, 23, 24 ACW..................................................................................................................................................19, 24 ADS.................................................................................................................................13, 27, 28, 61, 62 AFS ...................................................................................................................................................19, 24 AIE.....................................................................................................................................................14, 20 AMS ..................................................................................................................................................19, 24 ASP ...................................................................................................................................................19, 24
B
BCH ..................................................................................................................................................19, 45 BCV...................................................................................................................................................19, 45 BFH ...................................................................................................................................................19, 45 BFV ...................................................................................................................................................19, 45 BGA ............................................................................................................................................19, 60, 64 BPH...................................................................................................................................................19, 36 BPV .............................................................................................................................................19, 36, 37
C
CBH ............................................................................................................................................19, 48, 49 CBS.............................................................................................................................................15, 16, 20 CBV.............................................................................................................................................19, 48, 49 CDN ............................................................................................................................................20, 48, 51 CDO ............................................................................................................................................20, 47, 51 CGH ........................................................................................................................................................19 CGV ........................................................................................................................................................19 COV ............................................................................................................................................20, 33, 42 CPV.........................................................................................................................................................35 CRH ........................................................................................................................................................19 CRV ........................................................................................................................................................19
D
DCB ........................................................................................................................................................19 DCT...................................................................................................................................................19, 41 DHV ............................................................................................................................................20, 49, 50 DIG ....................................................................................................................................................19, 55 DIO ....................................................................................................................................................19, 55
E
EEPROMadd...........................................................................................................20, 27, 29, 61, 62, 63
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STV2050A - INDEX OF IC BUS REGISTERS ELO ...................................................................................................................................................20, 56 External PLL ..........................................................................................................................................14
F
FAS ...................................................................................................................................................19, 43 FIN.....................................................................................................................................................19, 55 FSB ...................................................................................................................................................19, 52 FSO...................................................................................................................................................19, 47 FV1....................................................................................................................................................19, 52 FV2....................................................................................................................................................19, 52 FV3....................................................................................................................................................19, 52 FVR ...................................................................................................................................................19, 52
G
GAH ............................................................................................................................................19, 20, 57 GAV ............................................................................................................................................19, 20, 57 GCD ............................................................................................................................................20, 49, 50 GCH ..................................................................................................................................................19, 45 GCP ..................................................................................................................................................20, 37 GCV ..................................................................................................................................................19, 45 GFH ..................................................................................................................................................19, 45 GFV...................................................................................................................................................19, 45 GLE .............................................................................................................................................19, 55, 56 GOS ......................................................................................................................................19, 20, 49, 56
H
HAE...................................................................................................................................................19, 42 HAM ............................................................................................................................................20, 61, 62 HBE...................................................................................................................................................19, 41 HDP ..................................................................................................................................................19, 23 HG1...................................................................................................................................................20, 39 HG2...................................................................................................................................................20, 39 HG3...................................................................................................................................................20, 59 HG4...................................................................................................................................................20, 59 HGD ................................................................................................................................19, 22, 23, 34, 41 HGP ..................................................................................................................................................19, 34 HIF.....................................................................................................................................................19, 47 HO1...................................................................................................................................................20, 39 HO2...................................................................................................................................................20, 39 HO3...................................................................................................................................................20, 59 HO4...................................................................................................................................................20, 59 HRD ............................................................................................................................................19, 22, 34 HVB.............................................................................................................................................19, 41, 42
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STV2050A - INDEX OF IC BUS REGISTERS HVM ......................................................................................................................................19, 20, 49, 56
I
ICV ....................................................................................................................................................19, 46 IFA.....................................................................................................................................................19, 46 IIE ................................................................................................................................................19, 25, 46 Internal PLL ...........................................................................................................................................14
M
MLE...................................................................................................................................................19, 48 MLN ............................................................................................................................................19, 48, 55 MSY ........................................................................................................................................................20 MVB ......................................................................................................................................20, 48, 49, 50 MVG ......................................................................................................................................20, 48, 49, 50 MVR ......................................................................................................................................20, 48, 49, 50
N
NOM..................................................................................................................................................19, 55
O
OBH ..................................................................................................................................................19, 46 OBV ..................................................................................................................................................19, 46 ODS ..................................................................................................................................................20, 58 ODT ..................................................................................................................................................20, 59 OGH ..................................................................................................................................................19, 46 OGV ..................................................................................................................................................19, 46 OLE .............................................................................................................................................19, 55, 56 OOS ..................................................................................................................................................20, 59 OPI ....................................................................................................................................................20, 59 OPTT_PATTERN .................................................................................................................................59 ORG ........................................................................................................................................................46 ORH ........................................................................................................................................................19 ORV ..................................................................................................................................................19, 46
P
PAS .......................................................................................................................................20, 32, 35, 39 PBH...................................................................................................................................................19, 33 PBV ...................................................................................................................................................19, 33 PDA.............................................................................................................................................19, 20, 56 PDB.............................................................................................................................................19, 20, 56 PDC ............................................................................................................................................19, 20, 56 PIA...........................................................................................................................................................20
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STV2050A - INDEX OF IC BUS REGISTERS PIB...........................................................................................................................................................20 PIC ..........................................................................................................................................................20 PLT..............................................................................................................................................19, 20, 56 PMH ............................................................................................................................................19, 48, 49 PMV ............................................................................................................................................19, 48, 49 POA ............................................................................................................................................19, 20, 56 POB ............................................................................................................................................19, 20, 56 POC ............................................................................................................................................19, 20, 56 PPL ...................................................................................................................................................20, 62 PRS...................................................................................................................................................19, 21
R
RCH ..................................................................................................................................................19, 45 RCV ..................................................................................................................................................19, 45 RFH...................................................................................................................................................19, 45 RFV ...................................................................................................................................................19, 45 RRP ..................................................................................................................................................16, 20 RU1 .............................................................................................................................................20, 56, 63 RU2 .............................................................................................................................................20, 56, 63 RUE ..................................................................................................................................................20, 63 RWM ...............................................................................................................................20, 27, 28, 61, 62
S
S01....................................................................................................................................................20, 63 S02........................................................................................................................................20, 48, 56, 63 S03....................................................................................................................................................20, 56 S05....................................................................................................................................................20, 59 S09..........................................................................................................................................................20 S10....................................................................................................................................................20, 25 S11....................................................................................................................................................20, 59 S12..........................................................................................................................................................20 S13....................................................................................................................................................20, 25 S14....................................................................................................................................................20, 25 S19..........................................................................................................................................................20 SBH...................................................................................................................................................19, 45 SBV ...................................................................................................................................................19, 45 SGH ..................................................................................................................................................19, 45 SGV ..................................................................................................................................................19, 45 SRH ..................................................................................................................................................19, 45 SRV...................................................................................................................................................19, 45 SSE .........................................................................................................................................................20 STA .......................................................................................................................................19, 28, 29, 33 STL..............................................................................................................................................20, 54, 56
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STV2050A - INDEX OF IC BUS REGISTERS STV2050A code....................................................................................................................................20 STX .......................................................................................................................................20, 27, 28, 29
T
TE2..........................................................................................................................................................20 TE4..........................................................................................................................................................20 TOL ...................................................................................................................................................19, 55 TVH .............................................................................................................................................19, 42, 43 TVV ...................................................................................................................................................19, 43
V
VAE ...................................................................................................................................................19, 42 VBE .........................................................................................................................................................19 VDC ..................................................................................................................................................20, 33 VFP ...................................................................................................................................................19, 52 VG1 ...................................................................................................................................................20, 39 VG2 ...................................................................................................................................................20, 39 VG3 ...................................................................................................................................................20, 59 VG4 ...................................................................................................................................................20, 59 VGD ......................................................................................................................................19, 34, 42, 52 VGP ............................................................................................................................................19, 34, 35 VHV...................................................................................................................................................20, 37 VO1 ...................................................................................................................................................20, 39 VO2 ...................................................................................................................................................20, 39 VO3 ...................................................................................................................................................20, 59 VO4 ...................................................................................................................................................20, 59 VST ...................................................................................................................................................19, 25 VVB .............................................................................................................................................19, 41, 42
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STV2050A - INDEX OF IC BUS REGISTERS
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